ttldtype.vhd

介绍数字滤波器的设计

END \7416\;

ARCHITECTURE model OF \7416\ IS

    BEGIN
    Y_A <= NOT ( I_A ) AFTER 23 ns;
    Y_B <= NOT ( I_B ) AFTER 23 ns;
    Y_C <= NOT ( I_C ) AFTER 23 ns;
    Y_D <= NOT ( I_D ) AFTER 23 ns;
    O_E <= NOT ( I_E ) AFTER 23 ns;
    O_F <= NOT ( I_F ) AFTER 23 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7417\ IS PORT(
I_A : IN  std_logic;
I_B : IN  std_logic;
I_C : IN  std_logic;
I_D : IN  std_logic;
I_E : IN  std_logic;
I_F : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
O_E : OUT  std_logic;
O_F : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7417\;

ARCHITECTURE model OF \7417\ IS

    BEGIN
    Y_A <=  ( I_A ) AFTER 30 ns;
    Y_B <=  ( I_B ) AFTER 30 ns;
    Y_C <=  ( I_C ) AFTER 30 ns;
    Y_D <=  ( I_D ) AFTER 30 ns;
    O_E <=  ( I_E ) AFTER 30 ns;
    O_F <=  ( I_F ) AFTER 30 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7420\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
D_A : IN  std_logic;
D_B : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7420\;

ARCHITECTURE model OF \7420\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A AND C_A AND D_A ) AFTER 22 ns;
    Y_B <= NOT ( A_B AND B_B AND C_B AND D_B ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7421\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
D_A : IN  std_logic;
D_B : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7421\;

ARCHITECTURE model OF \7421\ IS

    BEGIN
    Y_A <=  ( A_A AND B_A AND C_A AND D_A ) AFTER 27 ns;
    Y_B <=  ( A_B AND B_B AND C_B AND D_B ) AFTER 27 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7422\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
D_A : IN  std_logic;
D_B : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7422\;

ARCHITECTURE model OF \7422\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A AND C_A AND D_A ) AFTER 45 ns;
    Y_B <= NOT ( A_B AND B_B AND C_B AND D_B ) AFTER 45 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7425\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
D_A : IN  std_logic;
D_B : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
VCC : IN  std_logic;
G_A : IN  std_logic;
G_B : IN  std_logic;
GND : IN  std_logic);
END \7425\;

ARCHITECTURE model OF \7425\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL L5 : std_logic;
    SIGNAL L6 : std_logic;
    SIGNAL L7 : std_logic;
    SIGNAL L8 : std_logic;

    BEGIN
    L1 <=  ( A_A AND G_A );
    L2 <=  ( B_A AND G_A );
    L3 <=  ( C_A AND G_A );
    L4 <=  ( D_A AND G_A );
    L5 <=  ( A_B AND G_B );
    L6 <=  ( B_B AND G_B );
    L7 <=  ( C_B AND G_B );
    L8 <=  ( D_B AND G_B );
    Y_A <= NOT ( L1 OR L2 OR L3 OR L4 ) AFTER 22 ns;
    Y_B <= NOT ( L5 OR L6 OR L7 OR L8 ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7426\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7426\;

ARCHITECTURE model OF \7426\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A ) AFTER 24 ns;
    Y_B <= NOT ( A_B AND B_B ) AFTER 24 ns;
    Y_C <= NOT ( A_C AND B_C ) AFTER 24 ns;
    Y_D <= NOT ( B_D AND A_D ) AFTER 24 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7427\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
C_C : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7427\;

ARCHITECTURE model OF \7427\ IS

    BEGIN
    Y_A <= NOT ( A_A OR B_A OR C_A ) AFTER 15 ns;
    Y_B <= NOT ( A_B OR B_B OR C_B ) AFTER 15 ns;
    Y_C <= NOT ( C_C OR B_C OR A_C ) AFTER 15 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7428\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7428\;

ARCHITECTURE model OF \7428\ IS

    BEGIN
    Y_A <= NOT ( A_A OR B_A ) AFTER 12 ns;
    Y_B <= NOT ( A_B OR B_B ) AFTER 12 ns;
    Y_C <= NOT ( A_C OR B_C ) AFTER 12 ns;
    Y_D <= NOT ( A_D OR B_D ) AFTER 12 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7430\ IS PORT(
I0 : IN  std_logic;
I1 : IN  std_logic;
I2 : IN  std_logic;
I3 : IN  std_logic;
I4 : IN  std_logic;
I5 : IN  std_logic;
I6 : IN  std_logic;
I7 : IN  std_logic;
O : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7430\;

ARCHITECTURE model OF \7430\ IS

    BEGIN
    O <= NOT ( I0 AND I1 AND I2 AND I3 AND I4 AND I5 AND I6 AND I7 ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;



ENTITY \7432\ is
	PORT (
	A_A : IN std_logic;
	B_A : IN std_logic;
	Y_A : OUT std_logic;
	VCC : IN std_logic;
	GND : IN std_logic;
	A_B : IN std_logic;
	B_B : IN std_logic;
	Y_B : OUT std_logic;
	A_C : IN std_logic;
	B_C : IN std_logic;
	Y_C : OUT std_logic;
	A_D : IN std_logic;
	B_D : IN std_logic;
	Y_D : OUT std_logic
	); END \7432\;

ARCHITECTURE model OF \7432\ IS

    BEGIN
    Y_A <=  ( A_A OR B_A ) AFTER 22 ns;
    Y_B <=  ( A_B OR B_B ) AFTER 22 ns;
    Y_C <=  ( A_C OR B_C ) AFTER 22 ns;
    Y_D <=  ( A_D OR B_D ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7433\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7433\;

ARCHITECTURE model OF \7433\ IS

    BEGIN
    Y_A <= NOT ( A_A OR B_A ) AFTER 18 ns;
    Y_B <= NOT ( A_B OR B_B ) AFTER 18 ns;
    Y_C <= NOT ( A_C OR B_C ) AFTER 18 ns;
    Y_D <= NOT ( A_D OR B_D ) AFTER 18 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7437\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7437\;

ARCHITECTURE model OF \7437\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A ) AFTER 22 ns;
    Y_B <= NOT ( A_B AND B_B ) AFTER 22 ns;
    Y_C <= NOT ( A_C AND B_C ) AFTER 22 ns;
    Y_D <= NOT ( A_D AND B_D ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7438\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7438\;

ARCHITECTURE model OF \7438\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A ) AFTER 22 ns;
    Y_B <= NOT ( A_B AND B_B ) AFTER 22 ns;
    Y_C <= NOT ( A_C AND B_C ) AFTER 22 ns;
    Y_D <= NOT ( A_D AND B_D ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7439\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7439\;

ARCHITECTURE model OF \7439\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A ) AFTER 19 ns;
    Y_B <= NOT ( A_B AND B_B ) AFTER 19 ns;
    Y_C <= NOT ( A_C AND B_C ) AFTER 19 ns;
    Y_D <= NOT ( A_D AND B_D ) AFTER 19 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7440\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
D_A : IN  std_logic;
D_B : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7440\;

ARCHITECTURE model OF \7440\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A AND C_A AND D_A ) AFTER 22 ns;
    Y_B <= NOT ( D_B AND C_B AND B_B AND A_B ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7442\ IS PORT(
A : IN  std_logic;
B : IN  std_logic;
C : IN  std_logic;
D : IN  std_logic;
\0\ : OUT  std_logic;
\1\ : OUT  std_logic;
\2\ : OUT  std_logic;
\3\ : OUT  std_logic;
\4\ : OUT  std_logic;
\5\ : OUT  std_logic;
\6\ : OUT  std_logic;
\7\ : OUT  std_logic;
\8\ : OUT  std_logic;
\9\ : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7442\;

ARCHITECTURE model OF \7442\ IS
    SIGNAL N1 : std_logic;
    SIGNAL N2 : std_logic;
    SIGNAL N3 : std_logic;
    SIGNAL N4 : std_logic;
    SIGNAL N5 : std_logic;
    SIGNAL N6 : std_logic;
    SIGNAL N7 : std_logic;
    SIGNAL N8 : std_logic;

    BEGIN
    N1 <= NOT ( A ) AFTER 20 ns;
    N3 <= NOT ( B ) AFTER 20 ns;
    N5 <= NOT ( C ) AFTER 20 ns;