ttldtype.vhd

介绍数字滤波器的设计

--***************************************************************************
--*                                                                         *
--*                         Copyright (C) 1987-1995                         *
--*                              by OrCAD, INC.                             *
--*                                                                         *
--*                           All rights reserved.                          *
--*                                                                         *
--***************************************************************************
   
   
-- Purpose:		OrCAD VHDL Source File
-- Version:		v7.00.01
-- Date:			February 24, 1997
-- File:			TTL.VHD
-- Resource:	  National, Logic Data Book, 1984
-- Delay units:	  Nanoseconds 
-- Characteristics: 74XXXX MIN/MAX, Vcc=5V +/-0.5 V
 
-- Rev Notes:
--		x7.00.00 - Handle feedback in correct manner for Simulate v7.0 
--		v7.00.01 - Fixed components with Px port names.  



LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7400\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7400\;

ARCHITECTURE model OF \7400\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A ) AFTER 9 ns;
    Y_B <= NOT ( A_B AND B_B ) AFTER 9 ns;
    Y_C <= NOT ( B_C AND A_C ) AFTER 9 ns;
    Y_D <= NOT ( B_D AND A_D ) AFTER 9 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7401\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7401\;

ARCHITECTURE model OF \7401\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A ) AFTER 45 ns;
    Y_B <= NOT ( A_B AND B_B ) AFTER 45 ns;
    Y_C <= NOT ( A_C AND B_C ) AFTER 45 ns;
    Y_D <= NOT ( A_D AND B_D ) AFTER 45 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7402\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7402\;

ARCHITECTURE model OF \7402\ IS

    BEGIN
    Y_A <= NOT ( A_A OR B_A ) AFTER 22 ns;
    Y_B <= NOT ( A_B OR B_B ) AFTER 22 ns;
    Y_C <= NOT ( A_C OR B_C ) AFTER 22 ns;
    Y_D <= NOT ( A_D OR B_D ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7403\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7403\;

ARCHITECTURE model OF \7403\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A ) AFTER 45 ns;
    Y_B <= NOT ( A_B AND B_B ) AFTER 45 ns;
    Y_C <= NOT ( B_C AND A_C ) AFTER 45 ns;
    Y_D <= NOT ( B_D AND A_D ) AFTER 45 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7404\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
A_E : IN  std_logic;
A_F : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
Y_E : OUT  std_logic;
Y_F : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7404\;

ARCHITECTURE model OF \7404\ IS

    BEGIN
    Y_A <= NOT ( A_A ) AFTER 22 ns;
    Y_B <= NOT ( A_B ) AFTER 22 ns;
    Y_C <= NOT ( A_C ) AFTER 22 ns;
    Y_D <= NOT ( A_D ) AFTER 22 ns;
    Y_E <= NOT ( A_E ) AFTER 22 ns;
    Y_F <= NOT ( A_F ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7405\ IS PORT(
I_A : IN  std_logic;
I_B : IN  std_logic;
I_C : IN  std_logic;
I_D : IN  std_logic;
I_E : IN  std_logic;
I_F : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
O_E : OUT  std_logic;
O_F : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7405\;

ARCHITECTURE model OF \7405\ IS

    BEGIN
    Y_A <= NOT ( I_A ) AFTER 55 ns;
    Y_B <= NOT ( I_B ) AFTER 55 ns;
    Y_C <= NOT ( I_C ) AFTER 55 ns;
    Y_D <= NOT ( I_D ) AFTER 55 ns;
    O_E <= NOT ( I_E ) AFTER 55 ns;
    O_F <= NOT ( I_F ) AFTER 55 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7406\ IS PORT(
I_A : IN  std_logic;
I_B : IN  std_logic;
I_C : IN  std_logic;
I_D : IN  std_logic;
I_E : IN  std_logic;
I_F : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
O_E : OUT  std_logic;
O_F : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7406\;

ARCHITECTURE model OF \7406\ IS

    BEGIN
    Y_A <= NOT ( I_A ) AFTER 23 ns;
    Y_B <= NOT ( I_B ) AFTER 23 ns;
    Y_C <= NOT ( I_C ) AFTER 23 ns;
    Y_D <= NOT ( I_D ) AFTER 23 ns;
    O_E <= NOT ( I_E ) AFTER 23 ns;
    O_F <= NOT ( I_F ) AFTER 23 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7407\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
A_E : IN  std_logic;
A_F : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
Y_E : OUT  std_logic;
Y_F : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7407\;

ARCHITECTURE model OF \7407\ IS

    BEGIN
    Y_A <=  ( A_A ) AFTER 30 ns;
    Y_B <=  ( A_B ) AFTER 30 ns;
    Y_C <=  ( A_C ) AFTER 30 ns;
    Y_D <=  ( A_D ) AFTER 30 ns;
    Y_E <=  ( A_E ) AFTER 30 ns;
    Y_F <=  ( A_F ) AFTER 30 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7408\ is
	PORT (
	A_A : IN std_logic;
	B_A : IN std_logic;
	Y_A : OUT std_logic;
	VCC : IN std_logic;
	GND : IN std_logic;
	A_B : IN std_logic;
	B_B : IN std_logic;
	Y_B : OUT std_logic;
	A_C : IN std_logic;
	B_C : IN std_logic;
	Y_C : OUT std_logic;
	A_D : IN std_logic;
	B_D : IN std_logic;
	Y_D : OUT std_logic
	); END \7408\;

ARCHITECTURE model OF \7408\ IS

    BEGIN
    Y_A <=  ( A_A AND B_A ) AFTER 27 ns;
    Y_B <=  ( A_B AND B_B ) AFTER 27 ns;
    Y_C <=  ( A_C AND B_C ) AFTER 27 ns;
    Y_D <=  ( A_D AND B_D ) AFTER 27 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7409\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
A_D : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
B_D : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7409\;

ARCHITECTURE model OF \7409\ IS

    BEGIN
    Y_A <=  ( A_A AND B_A ) AFTER 32 ns;
    Y_B <=  ( A_B AND B_B ) AFTER 32 ns;
    Y_C <=  ( B_C AND A_C ) AFTER 32 ns;
    Y_D <=  ( B_D AND A_D ) AFTER 32 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7410\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
C_C : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7410\;

ARCHITECTURE model OF \7410\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A AND C_A ) AFTER 22 ns;
    Y_B <= NOT ( A_B AND B_B AND C_B ) AFTER 22 ns;
    Y_C <= NOT ( C_C AND B_C AND A_C ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7411\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
C_C : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7411\;

ARCHITECTURE model OF \7411\ IS

    BEGIN
    Y_A <=  ( A_A AND B_A AND C_A ) AFTER 27 ns;
    Y_B <=  ( A_B AND B_B AND C_B ) AFTER 27 ns;
    Y_C <=  ( C_C AND B_C AND A_C ) AFTER 27 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7412\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
A_C : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
B_C : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
C_C : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7412\;

ARCHITECTURE model OF \7412\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A AND C_A ) AFTER 45 ns;
    Y_B <= NOT ( A_B AND B_B AND C_B ) AFTER 45 ns;
    Y_C <= NOT ( C_C AND B_C AND A_C ) AFTER 45 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7413\ IS PORT(
A_A : IN  std_logic;
A_B : IN  std_logic;
B_A : IN  std_logic;
B_B : IN  std_logic;
C_A : IN  std_logic;
C_B : IN  std_logic;
D_A : IN  std_logic;
D_B : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7413\;

ARCHITECTURE model OF \7413\ IS

    BEGIN
    Y_A <= NOT ( A_A AND B_A AND C_A AND D_A ) AFTER 27 ns;
    Y_B <= NOT ( A_B AND B_B AND C_B AND D_B ) AFTER 27 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7414\ IS PORT(
I_A : IN  std_logic;
I_B : IN  std_logic;
I_C : IN  std_logic;
I_D : IN  std_logic;
I_E : IN  std_logic;
I_F : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
O_E : OUT  std_logic;
O_F : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \7414\;

ARCHITECTURE model OF \7414\ IS

    BEGIN
    Y_A <= NOT ( I_A ) AFTER 22 ns;
    Y_B <= NOT ( I_B ) AFTER 22 ns;
    Y_C <= NOT ( I_C ) AFTER 22 ns;
    Y_D <= NOT ( I_D ) AFTER 22 ns;
    O_E <= NOT ( I_E ) AFTER 22 ns;
    O_F <= NOT ( I_F ) AFTER 22 ns;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \7416\ IS PORT(
I_A : IN  std_logic;
I_B : IN  std_logic;
I_C : IN  std_logic;
I_D : IN  std_logic;
I_E : IN  std_logic;
I_F : IN  std_logic;
Y_A : OUT  std_logic;
Y_B : OUT  std_logic;
Y_C : OUT  std_logic;
Y_D : OUT  std_logic;
O_E : OUT  std_logic;
O_F : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);