finalbalancedfir.vhd

介绍数字滤波器的设计

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY FinalBalancedFIR IS PORT (
	Load : IN std_logic;
	Ct0 : OUT std_logic;
	Ct1 : OUT std_logic;
	nRST : IN std_logic;
	Ct2 : OUT std_logic;
	Ct3 : OUT std_logic;
	Total10 : OUT std_logic;
	Total11 : OUT std_logic;
	Total12 : OUT std_logic;
	Total13 : OUT std_logic;
	Total14 : OUT std_logic;
	Total15 : OUT std_logic;
	Qco0 : OUT std_logic;
	Qco1 : OUT std_logic;
	Qco2 : OUT std_logic;
	Qco3 : OUT std_logic;
	Qco4 : OUT std_logic;
	Qco5 : OUT std_logic;
	Qco6 : OUT std_logic;
	Qco7 : OUT std_logic;
	Dsg0 : IN std_logic;
	Dsg1 : IN std_logic;
	Dsg2 : IN std_logic;
	Dsg3 : IN std_logic;
	Dsg4 : IN std_logic;
	Dsg5 : IN std_logic;
	Dsg6 : IN std_logic;
	Dsg7 : IN std_logic;
	Total0 : OUT std_logic;
	Total1 : OUT std_logic;
	Total2 : OUT std_logic;
	Total3 : OUT std_logic;
	Total4 : OUT std_logic;
	Total5 : OUT std_logic;
	Total6 : OUT std_logic;
	Total7 : OUT std_logic;
	Total8 : OUT std_logic;
	Total9 : OUT std_logic;
	Clk : IN std_logic;
	nCt0 : OUT std_logic;
	nCt1 : OUT std_logic;
	nCt2 : OUT std_logic;
	nCt3 : OUT std_logic;
	Qsg0 : OUT std_logic;
	Qsg1 : OUT std_logic;
	Qsg2 : OUT std_logic;
	Qsg3 : OUT std_logic;
	Qsg4 : OUT std_logic;
	Qsg5 : OUT std_logic;
	Qsg6 : OUT std_logic;
	Qsg7 : OUT std_logic;
	Dco0 : IN std_logic;
	Dco1 : IN std_logic;
	Dco2 : IN std_logic;
	Dco3 : IN std_logic;
	Dco4 : IN std_logic;
	Dco5 : IN std_logic;
	Dco6 : IN std_logic;
	Dco7 : IN std_logic
); 

END FinalBalancedFIR;



ARCHITECTURE STRUCTURE OF FinalBalancedFIR IS

-- COMPONENTS

COMPONENT \16adderBalanced\
	PORT (
	A0 : IN std_logic;
	A1 : IN std_logic;
	A2 : IN std_logic;
	A3 : IN std_logic;
	A4 : IN std_logic;
	A5 : IN std_logic;
	A6 : IN std_logic;
	A7 : IN std_logic;
	A8 : IN std_logic;
	A9 : IN std_logic;
	A10 : IN std_logic;
	A11 : IN std_logic;
	A12 : IN std_logic;
	A13 : IN std_logic;
	A14 : IN std_logic;
	A15 : IN std_logic;
	B0 : IN std_logic;
	B1 : IN std_logic;
	B2 : IN std_logic;
	B3 : IN std_logic;
	B4 : IN std_logic;
	B5 : IN std_logic;
	B6 : IN std_logic;
	B7 : IN std_logic;
	B8 : IN std_logic;
	B9 : IN std_logic;
	B10 : IN std_logic;
	B11 : IN std_logic;
	B12 : IN std_logic;
	B13 : IN std_logic;
	B14 : IN std_logic;
	B15 : IN std_logic;
	CIN : IN std_logic;
	COUT : OUT std_logic;
	Y0 : OUT std_logic;
	Y1 : OUT std_logic;
	Y2 : OUT std_logic;
	Y3 : OUT std_logic;
	Y4 : OUT std_logic;
	Y5 : OUT std_logic;
	Y6 : OUT std_logic;
	Y7 : OUT std_logic;
	Y8 : OUT std_logic;
	Y9 : OUT std_logic;
	Y10 : OUT std_logic;
	Y11 : OUT std_logic;
	Y12 : OUT std_logic;
	Y13 : OUT std_logic;
	Y14 : OUT std_logic;
	Y15 : OUT std_logic
	); END COMPONENT;

COMPONENT NEWSLICE
	PORT (
	CLK : IN std_logic;
	DCO0 : IN std_logic;
	DCO1 : IN std_logic;
	DCO2 : IN std_logic;
	DCO3 : IN std_logic;
	DCO4 : IN std_logic;
	DCO5 : IN std_logic;
	DCO6 : IN std_logic;
	DCO7 : IN std_logic;
	DSG0 : IN std_logic;
	DSG1 : IN std_logic;
	DSG2 : IN std_logic;
	DSG3 : IN std_logic;
	DSG4 : IN std_logic;
	DSG5 : IN std_logic;
	DSG6 : IN std_logic;
	DSG7 : IN std_logic;
	ENABLE : IN std_logic;
	LOAD : IN std_logic;
	NRST : IN std_logic;
	QCO0 : OUT std_logic;
	QCO1 : OUT std_logic;
	QCO2 : OUT std_logic;
	QCO3 : OUT std_logic;
	QCO4 : OUT std_logic;
	QCO5 : OUT std_logic;
	QCO6 : OUT std_logic;
	QCO7 : OUT std_logic;
	QSG0 : OUT std_logic;
	QSG1 : OUT std_logic;
	QSG2 : OUT std_logic;
	QSG3 : OUT std_logic;
	QSG4 : OUT std_logic;
	QSG5 : OUT std_logic;
	QSG6 : OUT std_logic;
	QSG7 : OUT std_logic;
	S0 : OUT std_logic;
	S1 : OUT std_logic;
	S2 : OUT std_logic;
	S3 : OUT std_logic;
	S4 : OUT std_logic;
	S5 : OUT std_logic;
	S6 : OUT std_logic;
	S7 : OUT std_logic;
	S8 : OUT std_logic;
	S9 : OUT std_logic;
	S10 : OUT std_logic;
	S11 : OUT std_logic;
	S12 : OUT std_logic;
	S13 : OUT std_logic;
	S14 : OUT std_logic;
	S15 : OUT std_logic;
	SIGNED : OUT std_logic
	); END COMPONENT;

COMPONENT EIGHTBITREG
	PORT (
	CLK : IN std_logic;
	D0 : IN std_logic;
	D1 : IN std_logic;
	D2 : IN std_logic;
	D3 : IN std_logic;
	D4 : IN std_logic;
	D5 : IN std_logic;
	D6 : IN std_logic;
	D7 : IN std_logic;
	NPRESET : IN std_logic;
	NRESET : IN std_logic;
	Q0 : OUT std_logic;
	Q1 : OUT std_logic;
	Q2 : OUT std_logic;
	Q3 : OUT std_logic;
	Q4 : OUT std_logic;
	Q5 : OUT std_logic;
	Q6 : OUT std_logic;
	Q7 : OUT std_logic
	); END COMPONENT;

COMPONENT ADDERDELAY
	PORT (
	DIN0 : IN std_logic;
	DIN1 : IN std_logic;
	DIN2 : IN std_logic;
	DIN3 : IN std_logic;
	DIN4 : IN std_logic;
	DIN5 : IN std_logic;
	DIN6 : IN std_logic;
	DIN7 : IN std_logic;
	DIN8 : IN std_logic;
	DIN9 : IN std_logic;
	DIN10 : IN std_logic;
	DIN11 : IN std_logic;
	DIN12 : IN std_logic;
	DIN13 : IN std_logic;
	DIN14 : IN std_logic;
	DIN15 : IN std_logic;
	DOUT0 : OUT std_logic;
	DOUT1 : OUT std_logic;
	DOUT2 : OUT std_logic;
	DOUT3 : OUT std_logic;
	DOUT4 : OUT std_logic;
	DOUT5 : OUT std_logic;
	DOUT6 : OUT std_logic;
	DOUT7 : OUT std_logic;
	DOUT8 : OUT std_logic;
	DOUT9 : OUT std_logic;
	DOUT10 : OUT std_logic;
	DOUT11 : OUT std_logic;
	DOUT12 : OUT std_logic;
	DOUT13 : OUT std_logic;
	DOUT14 : OUT std_logic;
	DOUT15 : OUT std_logic;
	SIGNEDIN : IN std_logic;
	SIGNEDOUT : OUT std_logic
	); END COMPONENT;

COMPONENT TAPADDER
	PORT (
	A0 : IN std_logic;
	A1 : IN std_logic;
	A2 : IN std_logic;
	A3 : IN std_logic;
	A4 : IN std_logic;
	A5 : IN std_logic;
	A6 : IN std_logic;
	A7 : IN std_logic;
	A8 : IN std_logic;
	A9 : IN std_logic;
	A10 : IN std_logic;
	A11 : IN std_logic;
	A12 : IN std_logic;
	A13 : IN std_logic;
	A14 : IN std_logic;
	A15 : IN std_logic;
	AND1 : IN std_logic;
	AND2 : IN std_logic;
	AND3 : IN std_logic;
	B0 : IN std_logic;
	B1 : IN std_logic;
	B2 : IN std_logic;
	B3 : IN std_logic;
	B4 : IN std_logic;
	B5 : IN std_logic;
	B6 : IN std_logic;
	B7 : IN std_logic;
	B8 : IN std_logic;
	B9 : IN std_logic;
	B10 : IN std_logic;
	B11 : IN std_logic;
	B12 : IN std_logic;
	B13 : IN std_logic;
	B14 : IN std_logic;
	B15 : IN std_logic;
	CIN : IN std_logic;
	COUT : OUT std_logic;
	O0 : OUT std_logic;
	O1 : OUT std_logic;
	O2 : OUT std_logic;
	O3 : OUT std_logic;
	O4 : OUT std_logic;
	O5 : OUT std_logic;
	O6 : OUT std_logic;
	O7 : OUT std_logic;
	O8 : OUT std_logic;
	O9 : OUT std_logic;
	O10 : OUT std_logic;
	O11 : OUT std_logic;
	O12 : OUT std_logic;
	O13 : OUT std_logic;
	O14 : OUT std_logic;
	O15 : OUT std_logic;
	OR1 : IN std_logic;
	OR2 : IN std_logic;
	OR3 : IN std_logic;
	Y0 : OUT std_logic;
	Y1 : OUT std_logic;
	Y2 : OUT std_logic;
	Y3 : OUT std_logic;
	Y4 : OUT std_logic;
	Y5 : OUT std_logic;
	Y6 : OUT std_logic;
	Y7 : OUT std_logic;
	Y8 : OUT std_logic;
	Y9 : OUT std_logic;
	Y10 : OUT std_logic;
	Y11 : OUT std_logic;
	Y12 : OUT std_logic;
	Y13 : OUT std_logic;
	Y14 : OUT std_logic;
	Y15 : OUT std_logic
	); END COMPONENT;

COMPONENT COUNTER
	PORT (
	CLK : IN std_logic;
	NCLR : IN std_logic;
	NPRE : IN std_logic;
	NQ0 : OUT std_logic;
	NQ1 : OUT std_logic;
	NQ2 : OUT std_logic;
	NQ3 : OUT std_logic;
	Q0 : OUT std_logic;
	Q1 : OUT std_logic;
	Q2 : OUT std_logic;
	Q3 : OUT std_logic
	); END COMPONENT;

COMPONENT ORBLOCK
	PORT (
	A0 : INOUT std_logic;
	A1 : INOUT std_logic;
	A2 : INOUT std_logic;
	A3 : INOUT std_logic;
	A4 : INOUT std_logic;
	A5 : INOUT std_logic;
	A6 : INOUT std_logic;
	A7 : INOUT std_logic;
	A8 : INOUT std_logic;
	A9 : INOUT std_logic;
	A10 : INOUT std_logic;
	A11 : INOUT std_logic;
	A12 : INOUT std_logic;
	A13 : INOUT std_logic;
	A14 : INOUT std_logic;
	A15 : INOUT std_logic;
	B0 : INOUT std_logic;
	B1 : INOUT std_logic;
	B2 : INOUT std_logic;
	B3 : INOUT std_logic;
	B4 : INOUT std_logic;
	B5 : INOUT std_logic;
	B6 : INOUT std_logic;
	B7 : INOUT std_logic;
	B8 : INOUT std_logic;
	B9 : INOUT std_logic;
	B10 : INOUT std_logic;
	B11 : INOUT std_logic;
	B12 : INOUT std_logic;
	B13 : INOUT std_logic;
	B14 : INOUT std_logic;
	B15 : INOUT std_logic;
	C0 : INOUT std_logic;
	C1 : INOUT std_logic;
	C2 : INOUT std_logic;
	C3 : INOUT std_logic;
	C4 : INOUT std_logic;
	C5 : INOUT std_logic;
	C6 : INOUT std_logic;
	C7 : INOUT std_logic;
	C8 : INOUT std_logic;
	C9 : INOUT std_logic;
	C10 : INOUT std_logic;
	C11 : INOUT std_logic;
	C12 : INOUT std_logic;
	C13 : INOUT std_logic;
	C14 : INOUT std_logic;
	C15 : INOUT std_logic;
	D0 : INOUT std_logic;
	D1 : INOUT std_logic;
	D2 : INOUT std_logic;
	D3 : INOUT std_logic;
	D4 : INOUT std_logic;
	D5 : INOUT std_logic;
	D6 : INOUT std_logic;
	D7 : INOUT std_logic;
	D8 : INOUT std_logic;
	D9 : INOUT std_logic;
	D10 : INOUT std_logic;
	D11 : INOUT std_logic;
	D12 : INOUT std_logic;
	D13 : INOUT std_logic;
	D14 : INOUT std_logic;
	D15 : INOUT std_logic;
	E0 : INOUT std_logic;
	E1 : INOUT std_logic;
	E2 : INOUT std_logic;
	E3 : INOUT std_logic;
	E4 : INOUT std_logic;
	E5 : INOUT std_logic;
	E6 : INOUT std_logic;
	E7 : INOUT std_logic;
	E8 : INOUT std_logic;
	E9 : INOUT std_logic;
	E10 : INOUT std_logic;
	E11 : INOUT std_logic;
	E12 : INOUT std_logic;
	E13 : INOUT std_logic;
	E14 : INOUT std_logic;
	E15 : INOUT std_logic;
	F0 : INOUT std_logic;
	F1 : INOUT std_logic;
	F2 : INOUT std_logic;
	F3 : INOUT std_logic;
	F4 : INOUT std_logic;
	F5 : INOUT std_logic;
	F6 : INOUT std_logic;
	F7 : INOUT std_logic;
	F8 : INOUT std_logic;
	F9 : INOUT std_logic;
	F10 : INOUT std_logic;
	F11 : INOUT std_logic;
	F12 : INOUT std_logic;
	F13 : INOUT std_logic;
	F14 : INOUT std_logic;
	F15 : INOUT std_logic;
	G0 : INOUT std_logic;
	G1 : INOUT std_logic;
	G2 : INOUT std_logic;
	G3 : INOUT std_logic;
	G4 : INOUT std_logic;
	G5 : INOUT std_logic;
	G6 : INOUT std_logic;
	G7 : INOUT std_logic;
	G8 : INOUT std_logic;
	G9 : INOUT std_logic;
	G10 : INOUT std_logic;
	G11 : INOUT std_logic;
	G12 : INOUT std_logic;
	G13 : INOUT std_logic;
	G14 : INOUT std_logic;
	G15 : INOUT std_logic;
	H0 : INOUT std_logic;
	H1 : INOUT std_logic;
	H2 : INOUT std_logic;
	H3 : INOUT std_logic;
	H4 : INOUT std_logic;