hc.vhd

介绍数字滤波器的设计

    L5 <= NOT ( \5\ );
    L6 <= NOT ( \6\ );
    L7 <= NOT ( \7\ );
    L8 <=  ( \8\ AND \9\ );
    L9 <= NOT ( \9\ );
    L10 <= NOT ( L1 AND L8 AND \4\ AND \6\ AND \2\ );
    L11 <= NOT ( L3 AND L8 AND \4\ AND \6\ );
    L12 <= NOT ( L5 AND L8 AND \6\ );
    L13 <= NOT ( L7 AND L8 );
    L14 <= NOT ( L2 AND L8 AND \4\ AND \5\ );
    L15 <= NOT ( L3 AND L8 AND \4\ AND \5\ );
    L16 <= NOT ( L6 AND L8 );
    L17 <= NOT ( L4 AND L8 );
    L18 <= NOT ( L5 AND L8 );
    D <=  ( L8 ) AFTER 3800 ps;
    C <=  ( L13 AND L16 AND L17 AND L18 ) AFTER 3800 ps;
    B <=  ( L13 AND L14 AND L15 AND L16 ) AFTER 3800 ps;
    A <=  ( L10 AND L11 AND L12 AND L13 AND \9\ ) AFTER 3800 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC148\ IS PORT(
\0\ : IN  std_logic;
\1\ : IN  std_logic;
\2\ : IN  std_logic;
\3\ : IN  std_logic;
\4\ : IN  std_logic;
\5\ : IN  std_logic;
\6\ : IN  std_logic;
\7\ : IN  std_logic;
EI : IN  std_logic;
A0 : OUT  std_logic;
A1 : OUT  std_logic;
A2 : OUT  std_logic;
GS : OUT  std_logic;
EO : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \74HC148\;

ARCHITECTURE model OF \74HC148\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL L5 : std_logic;
    SIGNAL L6 : std_logic;
    SIGNAL L7 : std_logic;
    SIGNAL L8 : std_logic;
    SIGNAL L9 : std_logic;
    SIGNAL L10 : std_logic;
    SIGNAL L11 : std_logic;
    SIGNAL L12 : std_logic;
    SIGNAL L13 : std_logic;
    SIGNAL L14 : std_logic;
    SIGNAL L15 : std_logic;
    SIGNAL L16 : std_logic;
    SIGNAL L17 : std_logic;
    SIGNAL N1 : std_logic;
    SIGNAL N2 : std_logic;
    SIGNAL N3 : std_logic;
    SIGNAL N4 : std_logic;
    SIGNAL N5 : std_logic;
    SIGNAL N6 : std_logic;
    SIGNAL N7 : std_logic;
    SIGNAL N8 : std_logic;
    SIGNAL N9 : std_logic;
    SIGNAL N10 : std_logic;
    SIGNAL N11 : std_logic;
    SIGNAL N12 : std_logic;
    SIGNAL N13 : std_logic;
    SIGNAL N14 : std_logic;
    SIGNAL N15 : std_logic;
    SIGNAL N16 : std_logic;
    SIGNAL N17 : std_logic;
    SIGNAL N18 : std_logic;
    SIGNAL N19 : std_logic;

    BEGIN
    N1 <= NOT ( \1\ ) AFTER 500 ps;
    N2 <= NOT ( \2\ ) AFTER 500 ps;
    N3 <= NOT ( \3\ ) AFTER 500 ps;
    N4 <= NOT ( \4\ ) AFTER 500 ps;
    N5 <= NOT ( \5\ ) AFTER 500 ps;
    N6 <= NOT ( \6\ ) AFTER 500 ps;
    N7 <= NOT ( \7\ ) AFTER 500 ps;
    N8 <=  ( \1\ ) AFTER 1400 ps;
    N9 <=  ( \2\ ) AFTER 1400 ps;
    N10 <=  ( \3\ ) AFTER 1400 ps;
    N11 <=  ( \4\ ) AFTER 1400 ps;
    N12 <=  ( \5\ ) AFTER 1400 ps;
    N13 <=  ( \6\ ) AFTER 1400 ps;
    N14 <=  ( \7\ ) AFTER 1400 ps;
    N15 <=  ( \0\ ) AFTER 1400 ps;
    N16 <= NOT ( EI ) AFTER 900 ps;
    L1 <= NOT ( EI );
    L2 <= NOT ( N2 );
    L3 <= NOT ( N4 );
    L4 <= NOT ( N5 );
    L5 <= NOT ( N6 );
    L6 <=  ( L2 AND L3 AND L5 AND N1 AND N16 );
    L7 <=  ( L3 AND L5 AND N3 AND N16 );
    L8 <=  ( L5 AND N5 AND N16 );
    L9 <=  ( N7 AND N16 );
    L10 <=  ( L3 AND L4 AND N2 AND N16 );
    L11 <=  ( L3 AND L4 AND N3 AND N16 );
    L12 <=  ( N6 AND N16 );
    L13 <=  ( N7 AND N16 );
    L14 <=  ( N4 AND N16 );
    L15 <=  ( N5 AND N16 );
    L16 <=  ( N6 AND N16 );
    L17 <=  ( N7 AND N16 );
    N17 <=  ( L1 ) AFTER 200 ps;
    N18 <=  ( L1 ) AFTER 1700 ps;
    N19 <= NOT ( N8 AND N9 AND N10 AND N11 AND N12 AND N13 AND N14 AND N15 AND N17 ) AFTER 1400 ps;
    EO <= N19;    
    GS <= NOT ( N18 AND N19 ) AFTER 2400 ps;
    A0 <= NOT ( L6 OR L7 OR L8 OR L9 ) AFTER 3000 ps;
    A1 <= NOT ( L10 OR L11 OR L12 OR L13 ) AFTER 3000 ps;
    A2 <= NOT ( L14 OR L15 OR L16 OR L17 ) AFTER 3000 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC151\ IS PORT(
D0 : IN  std_logic;
D1 : IN  std_logic;
D2 : IN  std_logic;
D3 : IN  std_logic;
D4 : IN  std_logic;
D5 : IN  std_logic;
D6 : IN  std_logic;
D7 : IN  std_logic;
A : IN  std_logic;
B : IN  std_logic;
C : IN  std_logic;
G : IN  std_logic;
W : OUT  std_logic;
Y : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \74HC151\;

ARCHITECTURE model OF \74HC151\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL L5 : std_logic;
    SIGNAL N1 : std_logic;
    SIGNAL N2 : std_logic;
    SIGNAL N3 : std_logic;
    SIGNAL N4 : std_logic;
    SIGNAL N5 : std_logic;
    SIGNAL N6 : std_logic;
    SIGNAL N7 : std_logic;
    SIGNAL N8 : std_logic;
    SIGNAL N9 : std_logic;
    SIGNAL N10 : std_logic;
    SIGNAL N11 : std_logic;
    SIGNAL N12 : std_logic;

    BEGIN
    N1 <= NOT ( A ) AFTER 600 ps;
    N2 <= NOT ( B ) AFTER 600 ps;
    N3 <= NOT ( C ) AFTER 600 ps;
    N4 <= NOT ( G ) AFTER 200 ps;
    L1 <= NOT ( N1 );
    L2 <= NOT ( N2 );
    L3 <= NOT ( N3 );
    N5 <=  ( N1 AND N2 AND N3 AND D0 ) AFTER 800 ps;
    N6 <=  ( L1 AND N2 AND N3 AND D1 ) AFTER 800 ps;
    N7 <=  ( L2 AND N1 AND N3 AND D2 ) AFTER 800 ps;
    N8 <=  ( L1 AND L2 AND N3 AND D3 ) AFTER 800 ps;
    N9 <=  ( L3 AND N1 AND N2 AND D4 ) AFTER 800 ps;
    N10 <=  ( L1 AND L3 AND N2 AND D5 ) AFTER 800 ps;
    N11 <=  ( L2 AND L3 AND N1 AND D6 ) AFTER 800 ps;
    N12 <=  ( L1 AND L2 AND L3 AND D7 ) AFTER 800 ps;
    L4 <=  ( N5 OR N6 OR N7 OR N8 OR N9 OR N10 OR N11 OR N12 );
    L5 <= NOT ( L4 );
    Y <=  ( L4 AND N4 ) AFTER 2100 ps;
    W <=  ( L5 OR G ) AFTER 2100 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC152\ IS PORT(
D0 : IN  std_logic;
D1 : IN  std_logic;
D2 : IN  std_logic;
D3 : IN  std_logic;
D4 : IN  std_logic;
D5 : IN  std_logic;
D6 : IN  std_logic;
D7 : IN  std_logic;
A : IN  std_logic;
B : IN  std_logic;
C : IN  std_logic;
W : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \74HC152\;

ARCHITECTURE model OF \74HC152\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL L5 : std_logic;
    SIGNAL L6 : std_logic;
    SIGNAL L7 : std_logic;
    SIGNAL L8 : std_logic;
    SIGNAL L9 : std_logic;
    SIGNAL L10 : std_logic;
    SIGNAL L11 : std_logic;
    SIGNAL N1 : std_logic;
    SIGNAL N2 : std_logic;
    SIGNAL N3 : std_logic;

    BEGIN
    N1 <= NOT ( A ) AFTER 1000 ps;
    N2 <= NOT ( B ) AFTER 1000 ps;
    N3 <= NOT ( C ) AFTER 1000 ps;
    L1 <= NOT ( N1 );
    L2 <= NOT ( N2 );
    L3 <= NOT ( N3 );
    L4 <=  ( N1 AND N2 AND N3 AND D0 );
    L5 <=  ( L1 AND N2 AND N3 AND D1 );
    L6 <=  ( L2 AND N1 AND N3 AND D2 );
    L7 <=  ( L1 AND L2 AND N3 AND D3 );
    L8 <=  ( L3 AND N1 AND N2 AND D4 );
    L9 <=  ( L1 AND L3 AND N2 AND D5 );
    L10 <=  ( L2 AND L3 AND N1 AND D6 );
    L11 <=  ( L1 AND L2 AND L3 AND D7 );
    W <= NOT ( L4 OR L5 OR L6 OR L7 OR L8 OR L9 OR L10 OR L11 ) AFTER 3300 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC153\ IS PORT(
\1C0\ : IN  std_logic;
\1C1\ : IN  std_logic;
\1C2\ : IN  std_logic;
\1C3\ : IN  std_logic;
\2C0\ : IN  std_logic;
\2C1\ : IN  std_logic;
\2C2\ : IN  std_logic;
\2C3\ : IN  std_logic;
A : IN  std_logic;
B : IN  std_logic;
\1G\ : IN  std_logic;
\2G\ : IN  std_logic;
\1Y\ : OUT  std_logic;
\2Y\ : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \74HC153\;

ARCHITECTURE model OF \74HC153\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL L5 : std_logic;
    SIGNAL L6 : std_logic;
    SIGNAL L7 : std_logic;
    SIGNAL L8 : std_logic;
    SIGNAL L9 : std_logic;
    SIGNAL L10 : std_logic;
    SIGNAL N1 : std_logic;
    SIGNAL N2 : std_logic;
    SIGNAL N3 : std_logic;
    SIGNAL N4 : std_logic;
    SIGNAL N5 : std_logic;
    SIGNAL N6 : std_logic;

    BEGIN
    L1 <= NOT ( \1G\ );
    L2 <= NOT ( \2G\ );
    N1 <= NOT ( A ) AFTER 700 ps;
    N2 <= NOT ( B ) AFTER 700 ps;
    N3 <=  ( A ) AFTER 700 ps;
    N4 <=  ( B ) AFTER 700 ps;
    L3 <= NOT ( N3 AND N4 AND \1C3\ );
    L4 <= NOT ( N1 AND N4 AND \1C2\ );
    L5 <= NOT ( N2 AND N3 AND \1C1\ );
    L6 <= NOT ( N1 AND N2 AND \1C0\ );
    L7 <= NOT ( N3 AND N4 AND \2C3\ );
    L8 <= NOT ( N1 AND N4 AND \2C2\ );
    L9 <= NOT ( N2 AND N3 AND \2C1\ );
    L10 <= NOT ( N1 AND N2 AND \2C0\ );
    N5 <= NOT ( L3 AND L4 AND L5 AND L6 ) AFTER 800 ps;
    N6 <= NOT ( L7 AND L8 AND L9 AND L10 ) AFTER 800 ps;
    \1Y\ <=  ( L1 AND N5 ) AFTER 1500 ps;
    \2Y\ <=  ( L2 AND N6 ) AFTER 1500 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC154\ IS PORT(
A : IN  std_logic;
B : IN  std_logic;
C : IN  std_logic;
D : IN  std_logic;
G1 : IN  std_logic;
G2 : IN  std_logic;
\0\ : OUT  std_logic;
\1\ : OUT  std_logic;
\2\ : OUT  std_logic;
\3\ : OUT  std_logic;
\4\ : OUT  std_logic;
\5\ : OUT  std_logic;
\6\ : OUT  std_logic;
\7\ : OUT  std_logic;
\8\ : OUT  std_logic;
\9\ : OUT  std_logic;
\10\ : OUT  std_logic;
\11\ : OUT  std_logic;
\12\ : OUT  std_logic;
\13\ : OUT  std_logic;
\14\ : OUT  std_logic;
\15\ : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \74HC154\;

ARCHITECTURE model OF \74HC154\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL N1 : std_logic;
    SIGNAL N2 : std_logic;
    SIGNAL N3 : std_logic;
    SIGNAL N4 : std_logic;
    SIGNAL N5 : std_logic;

    BEGIN
    N1 <= NOT ( A ) AFTER 500 ps;
    N2 <= NOT ( B ) AFTER 500 ps;
    N3 <= NOT ( C ) AFTER 500 ps;
    N4 <= NOT ( D ) AFTER 500 ps;
    L1 <= NOT ( N1 );
    L2 <= NOT ( N2 );
    L3 <= NOT ( N3 );
    L4 <= NOT ( N4 );
    N5 <= NOT ( G1 OR G2 ) AFTER 500 ps;
    \0\ <= NOT ( N1 AND N2 AND N3 AND N4 AND N5 ) AFTER 3000 ps;
    \1\ <= NOT ( L1 AND N2 AND N3 AND N4 AND N5 ) AFTER 3000 ps;
    \2\ <= NOT ( L2 AND N1 AND N3 AND N4 AND N5 ) AFTER 3000 ps;
    \3\ <= NOT ( L1 AND L2 AND N3 AND N4 AND N5 ) AFTER 3000 ps;
    \4\ <= NOT ( L3 AND N1 AND N2 AND N4 AND N5 ) AFTER 3000 ps;
    \5\ <= NOT ( L1 AND L3 AND N2 AND N4 AND N5 ) AFTER 3000 ps;
    \6\ <= NOT ( L2 AND L3 AND N1 AND N4 AND N5 ) AFTER 3000 ps;
    \7\ <= NOT ( L1 AND L2 AND L3 AND N4 AND N5 ) AFTER 3000 ps;
    \8\ <= NOT ( L4 AND N1 AND N2 AND N3 AND N5 ) AFTER 3000 ps;
    \9\ <= NOT ( L1 AND L4 AND N2 AND N3 AND N5 ) AFTER 3000 ps;
    \10\ <= NOT ( L2 AND L4 AND N1 AND N3 AND N5 ) AFTER 3000 ps;
    \11\ <= NOT ( L1 AND L2 AND L4 AND N3 AND N5 ) AFTER 3000 ps;
    \12\ <= NOT ( L3 AND L4 AND N1 AND N2 AND N5 ) AFTER 3000 ps;
    \13\ <= NOT ( L1 AND L3 AND L4 AND N2 AND N5 ) AFTER 3000 ps;
    \14\ <= NOT ( L2 AND L3 AND L4 AND N1 AND N5 ) AFTER 3000 ps;
    \15\ <= NOT ( L1 AND L2 AND L3 AND L4 AND N5 ) AFTER 3000 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC157\ IS PORT(
\1A\ : IN  std_logic;
\1B\ : IN  std_logic;
\2A\ : IN  std_logic;
\2B\ : IN  std_logic;
\3A\ : IN  std_logic;
\3B\ : IN  std_logic;
\4A\ : IN  std_logic;
\4B\ : IN  std_logic;
\A\\/B\ : IN  std_logic;
G : IN  std_logic;
\1Y\ : OUT  std_logic;
\2Y\ : OUT  std_logic;
\3Y\ : OUT  std_logic;
\4Y\ : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \74HC157\;

ARCHITECTURE model OF \74HC157\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL L5 : std_logic;
    SIGNAL L6 : std_logic;
    SIGNAL L7 : std_logic;
    SIGNAL L8 : std_logic;
    SIGNAL L9 : std_logic;
    SIGNAL L10 : std_logic;
    SIGNAL L11 : std_logic;
    SIGNAL L12 : std_logic;

    BEGIN
    L1 <= NOT ( G );
    L2 <= NOT ( \A\\/B\ );
    L3 <=  ( L1 AND L2 );
    L4 <=  ( L1 AND \A\\/B\ );
    L5 <=  ( L3 AND \1A\ );
    L6 <=  ( L4 AND \1B\ );
    L7 <=  ( L3 AND \2A\ );
    L8 <=  ( L4 AND \2B\ );
    L9 <=  ( L3 AND \3A\ );
    L10 <=  ( L4 AND \3B\ );
    L11 <=  ( L3 AND \4A\ );
    L12 <=  ( L4 AND \4B\ );
    \1Y\ <=  ( L5 OR L6 ) AFTER 1900 ps;
    \2Y\ <=  ( L7 OR L8 ) AFTER 1900 ps;
    \3Y\ <=  ( L9 OR L10 ) AFTER 1900 ps;
    \4Y\ <=  ( L11 OR L12 ) AFTER 1900 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC157A\ IS PORT(
\1A\ : IN  std_logic;
\1B\ : IN  std_logic;
\2A\ : IN  std_logic;
\2B\ : IN  std_logic;
\3A\ : IN  std_logic;
\3B\ : IN  std_logic;
\4A\ : IN  std_logic;
\4B\ : IN  std_logic;
\A\\/B\ : IN  std_logic;
G : IN  std_logic;
\1Y\ : OUT  std_logic;
\2Y\ : OUT  std_logic;
\3Y\ : OUT  std_logic;
\4Y\ : OUT  std_logic;
VCC : IN  std_logic;
GND : IN  std_logic);
END \74HC157A\;

ARCHITECTURE model OF \74HC157A\ IS
    SIGNAL L1 : std_logic;
    SIGNAL L2 : std_logic;
    SIGNAL L3 : std_logic;
    SIGNAL L4 : std_logic;
    SIGNAL L5 : std_logic;
    SIGNAL L6 : std_logic;
    SIGNAL L7 : std_logic;
    SIGNAL L8 : std_logic;
    SIGNAL L9 : std_logic;
    SIGNAL L10 : std_logic;
    SIGNAL L11 : std_logic;
    SIGNAL L12 : std_logic;

    BEGIN
    L1 <= NOT ( G );
    L2 <= NOT ( \A\\/B\ );
    L3 <=  ( L1 AND L2 );
    L4 <=  ( L1 AND \A\\/B\ );
    L5 <=  ( L3 AND \1A\ );
    L6 <=  ( L4 AND \1B\ );
    L7 <=  ( L3 AND \2A\ );
    L8 <=  ( L4 AND \2B\ );
    L9 <=  ( L3 AND \3A\ );
    L10 <=  ( L4 AND \3B\ );
    L11 <=  ( L3 AND \4A\ );
    L12 <=  ( L4 AND \4B\ );
    \1Y\ <=  ( L5 OR L6 ) AFTER 1900 ps;
    \2Y\ <=  ( L7 OR L8 ) AFTER 1900 ps;
    \3Y\ <=  ( L9 OR L10 ) AFTER 1900 ps;
    \4Y\ <=  ( L11 OR L12 ) AFTER 1900 ps;
END model;


LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \74HC15