📄 start390.lst
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A51 MACRO ASSEMBLER START390 07/17/2003 18:04:05 PAGE 1
MACRO ASSEMBLER A51 V7.07
NO OBJECT MODULE REQUESTED
ASSEMBLER INVOKED BY: C:\KEIL\C51\BIN\A51.EXE ..\keilc51\Start390.a51 SET(LARGE) DEBUG PRINT(.\Start390.lst) OBJECT(.\St
art390.obj) EP
LOC OBJ LINE SOURCE
1 $nomod51
2 ;------------------------------------------------------------------------------
3 ; This file is part of the C51 Compiler package
4 ; Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
5 ; Startup code for Dallas 390/5240 CPU, Contigious Mode
6 ;------------------------------------------------------------------------------
7 ; START390.A51: This code is executed after processor reset.
8 ; You may add this file to a uVision2 project.
9 ;
10 ; To translate this file use A51 with the following invocation:
11 ;
12 ; AX51 START390.A51 MOD_CONT
13 ;
14 ; To link the modified STARTUP.OBJ file to your application use the following
15 ; LX51 invocation:
16 ;
17 ; LX51 <your object file list>, START390.OBJ <controls>
18 ;
19 ;------------------------------------------------------------------------------
20 ;
21 ; Chip Specific Options
22 ;
23 ; SA: Extend Stack Address Mode Enable (ACON.2)
0000 24 SA EQU 0 ; 0 = 8051 compatible stack in IDATA memory
25 ; ; 1 = Use 1KB stack in on-chip XDATA space
26 ;
27 ; IDM1, IDM0: Internal Data Memory Configuration Bits (MCON.7, MCON.6)
0000 28 IDM EQU 0 ; 0 = 4KB on-chip SRAM location X:0x00F000 - X:0x00FFFF
29 ; ; 1 = 4KB on-chip SRAM location X:0x000000 - X:0x000FFF
30 ; ; 2 = 4KB on-chip SRAM location X:0x400000 - X:0x400FFF
31 ; ; 3 = 4KB on-chip SRAM location X:0x400000 - X:0x400FFF
32 ; and code memory C:0x400000 - C:0x400FFF
33 ;
34 ; CMA: CAN Data Memory Assignment (MCON.5)
0000 35 CMA EQU 0 ; 0 = CAN0 X:0x00EE00 - X:0x00EEFF, CAN1 X:0x00EF00 - X:0x00EFFF
36 ; 1 = CAN0 X:0x401000 - X:0x4010FF, CAN1 X:0x401100 - X:0x4011FF
37 ;
38 ; PDCE3 .. PDCE0: Program/Data Chip Enable (MCON.3, MCON.2, MCON.1, MCON.0)
39 ; Program/Data Chip Enable selects whether the CEx signal functions as the chip
40 ; enable for external program memory only (PDCE=0), or as a merged chip enable
41 ; for program and data memory (PDCE=1).
0000 42 PDCE3 EQU 0 ; PDCE3=0: standard: RD signal for MOVX
43 ; PDCE3=1: von-Neumann: PSEN signal for MOVX
0000 44 PDCE2 EQU 0 ; PDCE2=0: standard: RD signal for MOVX
45 ; PDCE2=1: von-Neumann: PSEN signal for MOVX
0000 46 PDCE1 EQU 0 ; PDCE1=0: standard: RD signal for MOVX
47 ; PDCE1=1: von-Neumann: PSEN signal for MOVX
0000 48 PDCE0 EQU 0 ; PDCE0=0: standard: RD signal for MOVX
49 ; PDCE0=1: von-Neumann: PSEN signal for MOVX
50
51 ; Port 4 Function Control (P4CNT)
52 ; ===============================
53 ; Port 4 Pin Function (P4CNT.0 .. P4CNT.2)
0007 54 P4PF EQU 7 ; 0 : all pin used as I/O pin (P4.0 - P4.3)
55 ; ; 4 : P4.0 is CE0
56 ; ; 5 : P4.0 is CE0, P4.1 is CE1
57 ; ; 6 : P4.0 is CE0, P4.1 is CE1, P4.2 is CE2
A51 MACRO ASSEMBLER START390 07/17/2003 18:04:05 PAGE 2
58 ; ; 7 : P4.0 is CE0, P4.1 is CE1, P4.2 is CE2, P4.3 is CE3
59 ;
60 ; Program Memory Chip Enable Window Size (P4CNT.5 .. P4CNT.3)
0007 61 PCES EQU 7 ; 0 = 32KB address window (0 - 0x7FFF)
62 ; ; 4 = 128KB address window (0 - 0x1FFFF)
63 ; ; 5 = 256KB address window (0 - 0x3FFFF)
64 ; ; 6 = 512KB address window (0 - 0x7FFFF)
65 ; ; 7 = 1MB address window (0 - 0xFFFFF)
66 ;
67 ; Single CAN Configuration (P4CNT.6)
0000 68 SBCAN EQU 0 ; 1 = connects both CAN receive inputs and outputs to P5.0 and P5.1
69 ; 0 = both CAN interfaces work on their respective I/O pins
70
71 ; Port 5 Function Control (P5CNT)
72 ; ===============================
73 ; Serial Port 1 External Connections (P5CNT.5)
0000 74 SP1EC EQU 0 ; 0 = Serial Port is routed to P1.2/P1.3
75 ; ; 1 = Serial Port is routed to P5.2/P5.3
76 ;
77 ; Can I/O Enable (P5CNT.3 .. P5CNT.4)
0000 78 CX_IO EQU 0 ; 0 = P5.0 - P5.3 used as I/O pins
79 ; ; 1 = P5.2 & P5.3 used as I/O pins, P5.0 & P5.1 used by CAN0
80 ; ; 2 = P5.0 & P5.1 used as I/O pins, P5.2 & P5.3 used by CAN1;
81 ; ; 3 = P5.0 & P5.1 used by CAN0, P5.2 & P5.3 used by CAN1;
82 ;
83 ; Port 5 Pin Function (P5CNT.2 .. P5CNT.0)
0007 84 P5PF EQU 7 ; 0 : all pin used as I/O pin (P4.4,P5.5-P5.7)
85 ; ; 4 : P4.4 is PCE0
86 ; ; 5 : P4.4 is PCE0, P5.5 is PCE1
87 ; ; 6 : P4.4 is PCE0, P5.5 is PCE1, P5.6 is PCE2
88 ; ; 7 : P4.4 is PCE0, P5.5 is PCE1, P5.6 is PCE2, P5.7 is PCE3
89
90 ;
91 ;------------------------------------------------------------------------------
92 ;
93 ; User-defined Power-On Initialization of Memory
94 ;
95 ; With the following EQU statements the initialization of memory
96 ; at processor reset can be defined:
97 ;
98 ; ; the absolute start-address of IDATA memory is always 0
0080 99 IDATALEN EQU 80H ; the length of IDATA memory in bytes.
100 ;
0000 101 XDATASTART EQU 0H ; the absolute start-address of XDATA memory
0000 102 XDATALEN EQU 0H ; the length of XDATA memory in bytes.
103 ;
0000 104 PDATASTART EQU 0H ; the absolute start-address of PDATA memory
0000 105 PDATALEN EQU 0H ; the length of PDATA memory in bytes.
106 ;
107 ; Notes: The IDATA space overlaps physically the DATA and BIT areas of the
108 ; 8051 CPU. At minimum the memory space occupied from the C51
109 ; run-time routines must be set to zero.
110 ;------------------------------------------------------------------------------
111 ;
112 ; Reentrant Stack Initilization
113 ;
114 ; The following EQU statements define the stack pointer for reentrant
115 ; functions and initialized it:
116 ;
117 ; Stack Space for reentrant functions in the SMALL model.
0000 118 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
0100 119 IBPSTACKTOP EQU 0FFH+1 ; set top of stack to highest location+1.
120 ;
121 ; Stack Space for reentrant functions in the LARGE model.
0000 122 XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
0000 123 XBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.
A51 MACRO ASSEMBLER START390 07/17/2003 18:04:05 PAGE 3
124 ;
125 ; Stack Space for reentrant functions in the COMPACT model.
0000 126 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
0000 127 PBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.
128 ;
129 ;------------------------------------------------------------------------------
130 ;
131 ; Page Definition for Using the Compact Model with 64 KByte xdata RAM
132 ;
133 ; The following EQU statements define the xdata page used for pdata
134 ; variables. The EQU PPAGE must conform with the PPAGE control used
135 ; in the linker invocation.
136 ;
0000 137 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
0000 138 PPAGE EQU 0 ; define PPAGE number.
139 ;
140 ;------------------------------------------------------------------------------
141
142 ;#include <REG390.H>
+1 143
+1 144
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+1 150
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+1 153
+1 154
0080 +1 155 sfr P4 = 0x80;
0090 +1 156 sfr P1 = 0x90;
00A0 +1 157 sfr P2 = 0xA0;
00B0 +1 158 sfr P3 = 0xB0;
00D0 +1 159 sfr PSW = 0xD0;
00E0 +1 160 sfr ACC = 0xE0;
00F0 +1 161 sfr B = 0xF0;
0081 +1 162 sfr SP = 0x81;
0082 +1 163 sfr DPL = 0x82;
0083 +1 164 sfr DPH = 0x83;
0087 +1 165 sfr PCON = 0x87;
0088 +1 166 sfr TCON = 0x88;
0089 +1 167 sfr TMOD = 0x89;
008A +1 168 sfr TL0 = 0x8A;
008B +1 169 sfr TL1 = 0x8B;
008C +1 170 sfr TH0 = 0x8C;
008D +1 171 sfr TH1 = 0x8D;
00A8 +1 172 sfr IE = 0xA8;
00B8 +1 173 sfr IP = 0xB8;
0098 +1 174 sfr SCON0 = 0x98;
0099 +1 175 sfr SBUF0 = 0x99;
+1 176
+1 177
0084 +1 178 sfr DPL1 = 0x84;
0085 +1 179 sfr DPH1 = 0x85;
0086 +1 180 sfr DPS = 0x86;
008E +1 181 sfr CKCON = 0x8E;
0091 +1 182 sfr EXIF = 0x91;
0092 +1 183 sfr P4CNT = 0x92;
0093 +1 184 sfr DPX = 0x93;
0095 +1 185 sfr DPX1 = 0x95;
0096 +1 186 sfr C0RMS0 = 0x96;
0097 +1 187 sfr C0RMS1 = 0x97;
009B +1 188 sfr ESP = 0x9B;
009C +1 189 sfr AP = 0x9C;
A51 MACRO ASSEMBLER START390 07/17/2003 18:04:05 PAGE 4
009D +1 190 sfr ACON = 0x9D;
009E +1 191 sfr C0TMA0 = 0x9E;
009F +1 192 sfr C0TMA1 = 0x9F;
00A1 +1 193 sfr P5 = 0xA1;
00A2 +1 194 sfr P5CNT = 0xA2;
00A3 +1 195 sfr C0C = 0xA3;
00A4 +1 196 sfr C0S = 0xA4;
00A5 +1 197 sfr C0IR = 0xA5;
00A6 +1 198 sfr C0TE = 0xA6;
00A7 +1 199 sfr C0RE = 0xA7;
00A9 +1 200 sfr SADDR0 = 0xA9;
00AA +1 201 sfr SADDR1 = 0xAA;
00AB +1 202 sfr C0M1C = 0xAB;
00AC +1 203 sfr C0M2C = 0xAC;
00AD +1 204 sfr C0M3C = 0xAD;
00AE +1 205 sfr C0M4C = 0xAE;
00AF +1 206 sfr C0M5C = 0xAF;
00B3 +1 207 sfr C0M6C = 0xB3;
00B4 +1 208 sfr C0M7C = 0xB4;
00B5 +1 209 sfr C0M8C = 0xB5;
00B6 +1 210 sfr C0M9C = 0xB6;
00B7 +1 211 sfr C0M10C = 0xB7;
00B9 +1 212 sfr SADEN0 = 0xB9;
00BA +1 213 sfr SADEN1 = 0xBA;
00BB +1 214 sfr C0M11C = 0xBB;
00BC +1 215 sfr C0M12C = 0xBC;
00BD +1 216 sfr C0M13C = 0xBD;
00BE +1 217 sfr C0M14C = 0xBE;
00BF +1 218 sfr C0M15C = 0xBF;
00C0 +1 219 sfr SCON1 = 0xC0;
00C1 +1 220 sfr SBUF1 = 0xC1;
00C4 +1 221 sfr PMR = 0xC4;
00C5 +1 222 sfr STATUS = 0xC5;
00C6 +1 223 sfr MCON = 0xC6;
00C7 +1 224 sfr TA = 0xC7;
00C8 +1 225 sfr T2CON = 0xC8;
00C9 +1 226 sfr T2MOD = 0xC9;
00CA +1 227 sfr RCAP2L = 0xCA;
00CB +1 228 sfr RCAP2H = 0xCB;
00CC +1 229 sfr TL2 = 0xCC;
00CD +1 230 sfr TH2 = 0xCD;
00CE +1 231 sfr COR = 0xCE;
00D1 +1 232 sfr MCNT0 = 0xD1;
00D2 +1 233 sfr MCNT1 = 0xD2;
00D3 +1 234 sfr MA = 0xD3;
00D4 +1 235 sfr MB = 0xD4;
00D5 +1 236 sfr MC = 0xD5;
00D6 +1 237 sfr C1RMS0 = 0xD6;
00D7 +1 238 sfr C1RMS1 = 0xD7;
00D8 +1 239 sfr WDCON = 0xD8;
00DE +1 240 sfr C1TMA0 = 0xDE;
00DF +1 241 sfr C1TMA1 = 0xDF;
00E3 +1 242 sfr C1C = 0xE3;
00E4 +1 243 sfr C1S = 0xE4;
00E5 +1 244 sfr C1IR = 0xE5;
00E6 +1 245 sfr C1TE = 0xE6;
00E7 +1 246 sfr C1RE = 0xE7;
00E8 +1 247 sfr EIE = 0xE8;
00EA +1 248 sfr MXAX = 0xEA;
00EB +1 249 sfr C1M1C = 0xEB;
00EC +1 250 sfr C1M2C = 0xEC;
00ED +1 251 sfr C1M3C = 0xED;
00EE +1 252 sfr C1M4C = 0xEE;
00EF +1 253 sfr C1M5C = 0xEF;
00F3 +1 254 sfr C1M6C = 0xF3;
00F4 +1 255 sfr C1M7C = 0xF4;
A51 MACRO ASSEMBLER START390 07/17/2003 18:04:05 PAGE 5
00F5 +1 256 sfr C1M8C = 0xF5;
00F6 +1 257 sfr C1M9C = 0xF6;
00F7 +1 258 sfr C1M10C = 0xF7;
00F8 +1 259 sfr EIP = 0xF8;
00FB +1 260 sfr C1M11C = 0xFB;
00FC +1 261 sfr C1M12C = 0xFC;
00FD +1 262 sfr C1M13C = 0xFD;
00FE +1 263 sfr C1M14C = 0xFE;
00FF +1 264 sfr C1M15C = 0xFF;
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+1 267
0087 +1 268 sbit P4_7 = P4^7;
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