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📄 2410init.s

📁 ucCos移植到广州友善nano2410
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;=========================================
; NAME: 2410INIT.S
; DESC: C start up codes
;       Configure memory, ISR ,stacks
;	Initialize C-variables
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,POWER_OFF mode
; 2003.05.19:jcs:Configure UPLL in init.s not usbmain.c
;=========================================

	GET ..\inc\option.inc
	GET ..\inc\memcfg.inc
	GET ..\inc\2410addr.inc

BIT_SELFREFRESH EQU	(1<<22)

;Pre-defined constants
USERMODE    EQU 	0x10
FIQMODE     EQU 	0x11
IRQMODE     EQU 	0x12
SVCMODE     EQU 	0x13
ABORTMODE   EQU 	0x17
UNDEFMODE   EQU 	0x1b
MODEMASK    EQU 	0x1f
NOINT       EQU 	0xc0

;The location of stacks
UserStack	EQU	(_STACK_BASEADDRESS-0x3800)	;0x33ff4800 ~ 
SVCStack    EQU	(_STACK_BASEADDRESS-0x2800) 	;0x33ff5800 ~
UndefStack	EQU	(_STACK_BASEADDRESS-0x2400) 	;0x33ff5c00 ~
AbortStack	EQU	(_STACK_BASEADDRESS-0x2000) 	;0x33ff6000 ~
IRQStack    EQU	(_STACK_BASEADDRESS-0x1000)	;0x33ff7000 ~
FIQStack	EQU	(_STACK_BASEADDRESS-0x0)	;0x33ff8000 ~ 

;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
	GBLL    THUMBCODE
	[ {CONFIG} = 16 
THUMBCODE SETL  {TRUE}
	    CODE32
    	|   
THUMBCODE SETL  {FALSE}
    	]

    	MACRO
	MOV_PC_LR
    	[ THUMBCODE
            bx lr
    	|
            mov	pc,lr
    	]
	MEND

    	MACRO
	MOVEQ_PC_LR
    	[ THUMBCODE
    	    bxeq lr
    	|
            moveq pc,lr
    	]
	MEND

    	MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
	sub	sp,sp,#4        ;decrement sp(to store jump address)
	stmfd	sp!,{r0}        ;PUSH the work register to stack(lr does't push because it return to original address)
	ldr     r0,=$HandleLabel;load the address of HandleXXX to r0
	ldr     r0,[r0]         ;load the contents(service routine start address) of HandleXXX
	str     r0,[sp,#4]      ;store the contents(ISR) of HandleXXX to stack
	ldmfd   sp!,{r0,pc}     ;POP the work register and pc(jump to ISR)
	MEND
	
	IMPORT  |Image$$RO$$Base|
	IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
	IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise
	IMPORT 	|Image$$RW$$Limit|
	IMPORT  |Image$$ZI$$Base|   ; Base and limit of area
	IMPORT  |Image$$ZI$$Limit|  ; to zero initialise
	
	IMPORT  Main    ; The main entry of mon program 
	IMPORT  nand_read_ll
	
	AREA    Init,CODE,READONLY

	ENTRY 
    b	ResetHandler  
	b	HandlerUndef	;handler for Undefined mode
	b	HandlerSWI	;handler for SWI interrupt
	b	HandlerPabort	;handler for PAbort
	b	HandlerDabort	;handler for DAbort
	b	.		;reserved
	b	HandlerIRQ	;handler for IRQ interrupt 
	b	HandlerFIQ	;handler for FIQ interrupt

;@0x20
	b	EnterPWDN
	
;Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on. 
; 5. The location of the following code may have not to be changed.

;void EnterPWDN(int CLKCON); 
EnterPWDN			
	mov r2,r0		;r2=rCLKCON
	tst r0,#0x8		;POWER_OFF mode?
	bne ENTER_POWER_OFF

ENTER_STOP	
	ldr r0,=REFRESH		
	ldr r3,[r0]		;r3=rREFRESH	
	mov r1, r3
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]		;Enable SDRAM self-refresh

	mov r1,#16	   	;wait until self-refresh is issued. may not be needed.
0	subs r1,r1,#1
	bne %B0

	ldr r0,=CLKCON		;enter STOP mode.
	str r2,[r0]    

	mov r1,#32
0	subs r1,r1,#1	;1) wait until the STOP mode is in effect.
	bne %B0		;2) Or wait here until the CPU&Peripherals will be turned-off
			;   Entering POWER_OFF mode, only the reset by wake-up is available.

	ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
	str r3,[r0]
	
	MOV_PC_LR

ENTER_POWER_OFF	
	;NOTE.
	;1) rGSTATUS3 should have the return address after wake-up from POWER_OFF mode.
	
	ldr r0,=REFRESH		
	ldr r1,[r0]		;r1=rREFRESH	
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]		;Enable SDRAM self-refresh

	mov r1,#16	   	;Wait until self-refresh is issued,which may not be needed.
0	subs r1,r1,#1
	bne %B0

	ldr 	r1,=MISCCR
	ldr	r0,[r1]
	orr	r0,r0,#(7<<17)  ;Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up 
	str	r0,[r1]

	ldr r0,=CLKCON
	str r2,[r0]    

	b .			;CPU will die here.
	

WAKEUP_POWER_OFF
	;Release SCLKn after wake-up from the POWER_OFF mode.
    ;FND Off
	ldr r1, =GPACON  
	ldr r0, =0x7fffff
	str r0,[r1]
	
	ldr r1, =0x10000002
	ldr r0, =0x0000
	str r0,[r1]
	
	
	ldr	r1,=MISCCR
	ldr	r0,[r1]
	bic	r0,r0,#(7<<17)  ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
	str	r0,[r1]

	;Set memory control registers
    	ldr	r0,=SMRDATA
	ldr	r1,=BWSCON	;BWSCON Address
	add	r2, r0, #52	;End address of SMRDATA
0       
	ldr	r3, [r0], #4    
	str	r3, [r1], #4    
	cmp	r2, r0		
	bne	%B0

	mov r1,#256
0	subs r1,r1,#1	;1) wait until the SelfRefresh is released.
	bne %B0		
	
	ldr r1,=GSTATUS3 	;GSTATUS3 has the start address just after POWER_OFF wake-up
	ldr r0,[r1]
	mov pc,r0

	LTORG   
HandlerFIQ      HANDLER HandleFIQ
HandlerIRQ      HANDLER HandleIRQ
HandlerUndef    HANDLER HandleUndef
HandlerSWI      HANDLER HandleSWI
HandlerDabort   HANDLER HandleDabort
HandlerPabort   HANDLER HandlePabort

IsrIRQ  
	sub	sp,sp,#4       ;reserved for PC
	stmfd	sp!,{r8-r9}   
	
	ldr	r9,=INTOFFSET
	ldr	r9,[r9]
	ldr	r8,=HandleEINT0
	add	r8,r8,r9,lsl #2
	ldr	r8,[r8]
	str	r8,[sp,#8]
	ldmfd	sp!,{r8-r9,pc}

;=======
; ENTRY  
;=======
ResetHandler
	ldr	r0,=WTCON       ;watch dog disable 
	ldr	r1,=0x0         
	str	r1,[r0]

	ldr	r0,=INTMSK
	ldr	r1,=0xffffffff  ;all interrupt disable
	str	r1,[r0]

	ldr	r0,=INTSUBMSK
	ldr	r1,=0x3ff		;all sub interrupt disable
	str	r1,[r0]

    ;FND Display Off
	ldr	r0,=0x10000000
	ldr	r1,=0x0		
	str	r1,[r0]
	ldr	r0,=0x10000002
	ldr	r1,=0xff
	str	r1,[r0]
    
    ; Led Setting for fault Display
	ldr	r0,=GPFCON
	ldr	r1,=0x5500		
	str	r1,[r0]
	ldr	r0,=GPFDAT
	ldr	r1,=0x00
	str	r1,[r0]

	
	;To reduce PLL lock time, adjust the LOCKTIME register. 
	ldr	r0,=LOCKTIME
	mvn	r1, #0xff000000
	str	r1,[r0]
        
	mov	r1, #CLK_CTL_BASE	mov	r2, #0x03	str	r2, [r1, #oCLKDIVN]
	
	mrc	p15, 0, r1, c1, c0, 0		; read ctrl register 	orr	r1, r1, #0xc0000000		; Asynchronous  	mcr	p15, 0, r1, c1, c0, 0		; write ctrl register
	
	; now ,usb clock is set to 48Mhz	mov     r0, #CLK_CTL_BASE  ; Fin=12MHz, Fout=48MHz	ldr     r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)  ;Fin=12MHz,UPLLout=48MHz	str     r1, [r0,#oUPLLCON]  	nop 	nop 	nop 	nop 	;mov     r0, #CLK_CTL_BASE  ; Fin=12MHz, Fout=48MHz	;ldr     r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)  ;Fin=12MHz,UPLLout=48MHz	;str     r1, [r0,#oUPLLCON]
	
	;Configure MPLL
	mov	r1, #CLK_CTL_BASE
	ldr	r2, =((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)  ;Fin=12MHz,Fout=200MHz	str	r2, [r1, #oMPLLCON]

	EXPORT StartPointAfterPowerOffWakeUp
StartPointAfterPowerOffWakeUp

	;Set memory control registers
	adrl	r0, SMRDATA
	ldr	r1,=BWSCON	;BWSCON Address
	add	r2, r0, #52	;End address of SMRDATA
0       
	ldr	r3, [r0], #4    
	str	r3, [r1], #4    
	cmp	r2, r0		
	bne	%B0
	
	
   	;Initialize stacks
	bl	InitStacks
	
	; set GPIO for UART	mov	r1, #GPIO_CTL_BASE	add	r1, r1, #oGPIO_H	ldr	r2, =0x0016faaa		str	r2, [r1, #oGPIO_CON]	ldr	r2, =0x000007ff	str	r2, [r1, #oGPIO_UP]	
	
	bl	InitUART
	
	bl	copy_myself	;@ jump to ram	ldr	r1, =on_the_ram	add	pc, r1, #0	nop	nop
0	bne	%B0

on_the_ram

  	; Setup IRQ handler
	ldr	r0,=HandleIRQ       ;This routine is needed
	ldr	r1,=IsrIRQ          ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
	str	r1,[r0]

	;Copy and paste RW data/zero initialized data
	ldr	r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
	ldr	r1, =|Image$$RW$$Base|  ; and RAM copy
	ldr	r3, =|Image$$ZI$$Base|  
	
	;Zero init base => top of initialised data
	cmp	r0, r1      ; Check that they are different
	beq	%F2
1       
	cmp	r1, r3      ; Copy init data
	ldrcc	r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4         
	strcc	r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4
	bcc	%B1
2       
	ldr	r1, =|Image$$ZI$$Limit| ; Top of zero init segment
	mov	r2, #0
3       
	cmp	r3, r1      ; Zero init
	strcc	r2, [r3], #4
	bcc	%B3

   	bl	Main        ;Don't use main() because ......
   	b	.                       

    
;@;@ copy_myself: copy vivi to ram;@copy_myself	stmfd   sp!,{lr}
	;@ reset NAND	mov	r1, #NAND_CTL_BASE	ldr	r2, =0xf830		; initial value	str	r2, [r1, #oNFCONF]	ldr	r2, [r1, #oNFCONF]	bic	r2, r2, #0x800		;@ Active low CE Control @ enable chip	str	r2, [r1, #oNFCONF]	mov	r2, #0xff		;@ RESET command	strb	r2, [r1, #oNFCMD]	
	mov	r3, #0			;@ wait 1	add	r3, r3, #0x1	cmp	r3, #0xa	blt	%B12	ldr	r2, [r1, #oNFSTAT]	;@ wait ready	tst	r2, #0x1	beq	%B2	ldr	r2, [r1, #oNFCONF]	orr	r2, r2, #0x800		;@ disable chip	str	r2, [r1, #oNFCONF]	;@ get read to call C functions (for nand_read())	;ldr	sp, DW_STACK_START	;@ setup stack pointer
	;ldr	sp,=SVCStack		; SVCStack=0x33FF_5800	mov	fp, #0			;@ no previous frame, so fp=0	;@ copy vivi to RAM	ldr	    r0, =|Image$$RO$$Base|
	ldr     r2, =|Image$$RO$$Limit|	mov     r1, #0x0	
	;sub     r2,r2,r0 
	;mov	r2, #0x80000
	
	; RO	ldr r3, =|Image$$RO$$Limit|
	subs r2, r3, r0
	
	; RW
	ldr r3, =|Image$$RW$$Base|
	ldr r4, =|Image$$RW$$Limit|
	subs r3, r4, r3
	add r2, r2, r3
	
	;ZI
	ldr r3, =|Image$$ZI$$Base|
	ldr r4, =|Image$$ZI$$Limit|
	subs r3, r4, r3
	add r2, r2, r3	
	
;;//	mov	r2, #0xC0000
	
	bl	nand_read_ll	tst	r0, #0x0	beq	ok_nand_read
	bad_nand_read 	;ldr	r0, STR_FAIL	;ldr	r1, =UART0_CTL_BASE ;SerBase	;bl	PrintWord1	b	%B1		;@ infinite loop 	ok_nand_read    ;adrl	r0, STR_READNANDOK	;ldr	r1, =UART0_CTL_BASE ;SerBase	;bl	PrintStr    	;@ verify	mov	r0, #0	ldr	r1, =|Image$$RO$$Base|	mov	r2, #0x400	;@ 4 bytes * 1024 = 4K-bytesgo_next	ldr	r3, [r0], #4	ldr	r4, [r1], #4	teq	r3, r4	bne	notmatch	subs	r2, r2, #4	beq	done_nand_read		bne	go_nextnotmatch	;sub	r0, r0, #4	;ldr	r1, =UART0_CTL_BASE ;SerBase	;bl	PrintHexWord	;ldr	r0, STR_FAIL	;ldr	r1, =UART0_CTL_BASE ;SerBase	;bl	PrintWord
1	b	%B1done_nand_read	;adrl	r0, STR_COPYOK
	;ldr	r1, =UART0_CTL_BASE ;SerBase	;bl	PrintStr	mov	r1, #GPIO_CTL_BASE	add	r1, r1, #oGPIO_F	mov	r2, #0x40	str	r2, [r1, #oGPIO_DAT]	ldmfd   sp!,{pc}

; Initialize UART;; r0 = number of UART portInitUART	stmfd   sp!,{lr}		ldr	r1, =UART0_CTL_BASE	mov	r2, #0x0	str	r2, [r1, #oUFCON]	str	r2, [r1, #oUMCON]	mov	r2, #0x3	str	r2, [r1, #oULCON]	ldr	r2, =0x245	str	r2, [r1, #oUCON]UART_BRD    EQU     ((UART_PCLK  / (UART_BAUD_RATE * 16)) - 1)	mov	r2, #UART_BRD
	str	r2, [r1, #oUBRDIV]	mov	r3, #0xff1	sub	r3, r3, #0x1	teq	r3, #0x0	bne	%B1	mov	r0, #'U'	bl   PrintChar	mov	r0, #'0'	bl   PrintChar		mov	r0, #'\r'	bl   PrintChar		mov	r0, #'\n'	ldmfd   sp!,{lr}	b   PrintChar
	ldmfd   sp!,{pc}

;; Low Level Debug;; PrintChar : prints the character in R0;   r0 contains the character;   r1 contains base of serial port;   writes ro with XXX, modifies r0,r1,r2;   TODO : write ro with XXX reg to error handlingPrintChar	stmfd   sp!,{lr}	ldr	r1, =UART0_CTL_BASE1	ldr	r2, [r1, #oUTRSTAT]	tst	r2, #UTRSTAT_TX_EMPTY	beq	%B1	str	r0, [r1, #oUTXHL]
	ldmfd   sp!,{pc}


;==========================================
;function initializing stacks
InitStacks
	;Don't use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE|NOINT
	msr	cpsr_cxsf,r1		;UndefMode
	ldr	sp,=UndefStack
	
	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1		;AbortMode
	ldr	sp,=AbortStack

	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		;IRQMode
	ldr	sp,=IRQStack
    
	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1		;FIQMode
	ldr	sp,=FIQStack

	bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		;SVCMode
	ldr	sp,=SVCStack
	
	;USER mode has not be initialized.
	
	mov	pc,lr 
	;The LR register won't be valid if the current mode is not SVC mode.

LED_Flash
	ldr	r0,=GPFDAT
	ldr	r1,=0x10
	str	r1,[r0]
	
0
	mov r3,#0xff000
1   sub r3,r3,#1
    teq r3,#0
    bne %B1
    
    eor	r1,r1,#0x90
	str	r1,[r0]
	
    b %B0

	LTORG

SMRDATA ;DATA
; Memory configuration should be optimized for best performance 
; The following parameter is not optimized.                     
; Memory access cycle parameter strategy
; 1) The memory settings is  safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz. 

        DCD 0x21111110
    	DCD 0x00000700   ;GCS0
    	DCD 0x00000700   ;GCS1 
    	DCD 0x00000700   ;GCS2
    	DCD 0x00000700   ;GCS3
    	DCD 0x00000700   ;GCS4
    	DCD 0x00000700   ;GCS5
    	DCD 0x00018005   ;GCS6
    	DCD 0x00018005   ;GCS7
    	DCD 0x008e0459    

		DCD 0xb2            ;SCLK power saving mode, BANKSIZE 128M/128M

    	DCD 0x30            ;MRSR6 CL=3clk
    	DCD 0x30            ;MRSR7

    	ALIGN

    	AREA RamData, DATA, READWRITE

        ^   _ISR_STARTADDRESS
HandleReset 	#   4
HandleUndef 	#   4
HandleSWI   	#   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIRQ   	#   4
HandleFIQ   	#   4

;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
HandleEINT0   	#   4
HandleEINT1   	#   4
HandleEINT2   	#   4
HandleEINT3   	#   4
HandleEINT4_7	#   4
HandleEINT8_23	#   4
HandleRSV6	#   4
HandleBATFLT   	#   4
HandleTICK   	#   4
HandleWDT	#   4
HandleTIMER0 	#   4
HandleTIMER1 	#   4
HandleTIMER2 	#   4
HandleTIMER3 	#   4
HandleTIMER4 	#   4
HandleUART2  	#   4
HandleLCD 	#   4
HandleDMA0	#   4
HandleDMA1	#   4
HandleDMA2	#   4
HandleDMA3	#   4
HandleMMC	#   4
HandleSPI0	#   4
HandleUART1	#   4
HandleRSV24	#   4
HandleUSBD	#   4
HandleUSBH	#   4
HandleIIC   	#   4
HandleUART0 	#   4
HandleSPI1 	#   4
HandleRTC 	#   4
HandleADC 	#   4

        END

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