option.inc

ucCos移植到广州友善nano2410

;===========================================
; NAME: OPTION.A
; DESC: Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
;===========================================

;SDRAM_END			EQU	  0x32000000

;Start address of each stacks,
;_STACK_BASEADDRESS	EQU (SDRAM_END-0x8000)	;0x31ff8000
;_MMUTT_STARTADDRESS	EQU (SDRAM_END-0x8000)	;0x31ff8000
;_ISR_STARTADDRESS	EQU (SDRAM_END-0x100)	;0x31ffff00

;Start address of each stacks,
_STACK_BASEADDRESS	EQU 0x31ff8000  
_MMUTT_STARTADDRESS	EQU 0x31ff8000  
_ISR_STARTADDRESS	EQU 0x31ffff00

		GBLL 	PLL_ON_START  
PLL_ON_START	SETL 	{TRUE}


		GBLL	ENDIAN_CHANGE
ENDIAN_CHANGE	SETL	{FALSE}

		GBLA	ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH	SETA	16	


;BUSWIDTH = 16,32
		GBLA    BUSWIDTH	;max. bus width for the GPIO configuration
BUSWIDTH	SETA    16


		GBLL	CONFIG_S3C2410_NAND_BOOT
CONFIG_S3C2410_NAND_BOOT	SETL	{TRUE}
		GBLL	CONFIG_USE_UART
CONFIG_USE_UART	SETL	{TRUE}
		GBLL	CONFIG_DEBUG_LL
CONFIG_DEBUG_LL	SETL	{TRUE}

		GBLA	FCLK
FCLK		SETA	200000000

UART_PCLK 	    EQU	(FCLK/2/2)
UART_BAUD_RATE 	EQU	(115200)

	[ FCLK = 50000000	
M_MDIV		EQU	0x5c	;Fin=12.0MHz Fout=50.0MHz
M_PDIV		EQU	0x4
M_SDIV		EQU	0x2

U_MDIV		EQU	 40	;Fin=12.0MHz Fout=48.0MHz
U_PDIV		EQU	 1
U_SDIV		EQU	 2
    	]

    [ FCLK = 200000000	
M_MDIV		EQU	0x5c	;Fin=12.0MHz Fout=200.0MHz
M_PDIV		EQU	0x4
M_SDIV		EQU	0x0

U_MDIV		EQU	 40	;Fin=12.0MHz Fout=48.0MHz
U_PDIV		EQU	 1
U_SDIV		EQU	 2
    	]

	END