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📄 mypackage.vhd

📁 附件代码实现了基4FFT的碟形单元运算
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-- file name : mypackage.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;  

package mypackage is
 
	function signed_add (a,b:std_logic_vector) return std_logic_vector;
	function signed_sub (a,b:std_logic_vector) return std_logic_vector;
 	function signed_addf (a,b:std_logic_vector) return std_logic_vector;
	function signed_subf (a,b:std_logic_vector) return std_logic_vector;
	function Jexp (Pexp,ai,aq,bi,bq,ci,cq,di,dq:std_logic_vector) return std_logic_vector;
	
end mypackage;

package body mypackage is
 	
	-- 块浮点的指数值判决
	function Jexp (Pexp,ai,aq,bi,bq,ci,cq,di,dq:std_logic_vector) return std_logic_vector is
		variable Cexp :std_logic_vector(1 downto 0); -- 0~~3
		variable Ti,Tq,temp :std_logic_vector(2 downto 0);
	begin
		Ti := (ai or bi) or (ci or di);
		Tq := (aq or bq) or (cq or dq);
		temp := Ti or Tq;
		if(temp(2)='1') then -- 第一列有 1,溢出三位
			Cexp := "11";
		elsif(temp(1)='1') then	
			Cexp := "10";
		elsif(temp(0)='1') then	
			Cexp := "01";
		else Cexp := "00";
		end if;
		
		if Pexp >= Cexp then -- 非 3,即不是最大溢出
			return Pexp;
		else
			return Cexp;
		end if;
		
	end function Jexp;
		
	-- signed_add,结果做截位处理,位数没有扩张
	function signed_add (a,b:std_logic_vector) return std_logic_vector is
	    variable a_ext,b_ext  :std_logic_vector((a'high+1) downto 0);
    	variable sum          :std_logic_vector((a'high+1) downto 0); 
	begin
		a_ext := a(a'high)& a;  b_ext := b(a'high) & b; -- 符号扩展 
    	sum := a_ext + b_ext;
		return sum((a'high+1) downto 1);
	end function signed_add;
	
	-- signed_sub
	function signed_sub (a,b:std_logic_vector) return std_logic_vector is
		variable a_ext,b_ext  :std_logic_vector((a'high+1) downto 0);
    	variable diff         :std_logic_vector((a'high+1) downto 0); 
	begin
		a_ext := a(a'high)& a;  b_ext := b(a'high) & b; -- 符号扩展 
    	diff := a_ext - b_ext;
		return diff((a'high+1) downto 1);
	end function signed_sub;
	
	-- signed_addf ,结果位数扩张了一位
	function signed_addf (a,b:std_logic_vector) return std_logic_vector is
	    variable a_ext,b_ext  :std_logic_vector((a'high+1) downto 0);
    	variable sum          :std_logic_vector((a'high+1) downto 0); 
	begin
		a_ext := a(a'high)& a;  b_ext := b(a'high) & b; -- 符号扩展 
    	sum := a_ext + b_ext;
		return sum((a'high+1) downto 0);
	end function signed_addf;
	
	-- signed_subf
	function signed_subf (a,b:std_logic_vector) return std_logic_vector is
		variable a_ext,b_ext  :std_logic_vector((a'high+1) downto 0);
    	variable diff         :std_logic_vector((a'high+1) downto 0); 
	begin
		a_ext := a(a'high)& a;  b_ext := b(a'high) & b; -- 符号扩展 
    	diff := a_ext - b_ext;
		return diff((a'high+1) downto 0);
	end function signed_subf;
	
end package body;	    

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