butterfly.vhd

附件代码实现了基4FFT的碟形单元运算

--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version                           :1.0                   |
--*|Date of Last Revision             :12/23/1998            |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved.
--************************************************************
-- 实现流水操作，平均一个时钟处理一个蝶形
--************************************************************
--************************************************************

-- 输入数据17位=14+3（最多有3位衰减）
-- 增加指数判决，没有验证 12.2

library IEEE;
use IEEE.std_logic_1164.all;

-- library work;
use work.mypackage.all;
-- use work.all;


entity butterfly is
    generic(widthDAT:NATURAL :=16; widthRF :NATURAL :=16 );
    port(
        clk             :in std_logic;
        enable          :in std_logic;
        sin1,cos1     	:in std_logic_vector(widthRF-1 downto 0);
        sin2,cos2     	:in std_logic_vector(widthRF-1 downto 0);
        sin3,cos3     	:in std_logic_vector(widthRF-1 downto 0);    
        A,B,C,D         :in std_logic_vector(2*widthDAT-1 downto 0);
		expa			:in std_logic_vector(1 downto 0);
		G0,G1,G2,G3     :out std_logic_vector(2*widthDAT-1 downto 0);
		expb			:out std_logic_vector(1 downto 0); -- index: 0 ~~ 3
		finish			:out std_logic );
end butterfly;

architecture rtl of butterfly is

	constant Bit : NATURAL := widthDAT-1;
	constant Bit2 : NATURAL := 2*widthDAT-1;

 	signal AI,AQ,BI,BQ,CI,CQ,DI,DQ : std_logic_vector(widthDAT-4 downto 0);  
	signal S1,S2,S3,S4,S5,S6,S7,S8 : std_logic_vector(widthDAT-3 downto 0);
	signal R1,R2,R3,R4,R5,R6,R7,R8 : std_logic_vector(widthDAT-2 downto 0);
	signal cosw1,cosw2,cosw3   	   : std_logic_vector(widthRF-1 downto 0);
	signal sinw1,sinw2,sinw3   	   : std_logic_vector(widthRF-1 downto 0);
	
	signal e1,e2,e3,e4,e5,e6,e7,e8 : std_logic_vector(2 downto 0);
	signal enable0,enable1 : std_logic;
	signal GG0,GG1,GG2,GG3 : std_logic_vector(2*widthDAT-1 downto 0);
	
	attribute keep: boolean;
	attribute keep of enable0: signal is true;
	
	component ccmul 
    generic(widthDAT:NATURAL; widthRF :NATURAL);
    port( -- 输入输出位数不一致（widthDAT位-->）
        clk          :in std_logic;
		enable       :in std_logic;
        cos ,sin     :in std_logic_vector(widthRF-1 downto 0);
        Xre,Xim      :in std_logic_vector(widthDAT-1 downto 0);  -- 输入复数
        Y            :out std_logic_vector(2*widthDAT+1 downto 0));
	end component ;

begin 
  
	process(clk)
	begin
	if clk'event and clk = '1' then
		enable0 <= enable;
		enable1 <= enable0;
		finish <= enable;
	END IF;
	end process;
	
	process(expa,A,B,C,D)
	begin
	case expa is
	when "00" => AI <= A(2*widthDAT-4 downto widthDAT);AQ <= A(widthDAT-4 downto 0);
				  BI <= B(2*widthDAT-4 downto widthDAT);BQ <= B(widthDAT-4 downto 0);
				  CI <= C(2*widthDAT-4 downto widthDAT);CQ <= C(widthDAT-4 downto 0);
				  DI <= D(2*widthDAT-4 downto widthDAT);DQ <= D(widthDAT-4 downto 0);
	when "01" => AI <= A(2*widthDAT-3 downto widthDAT+1);AQ <= A(widthDAT-3 downto 1);
				  BI <= B(2*widthDAT-3 downto widthDAT+1);BQ <= B(widthDAT-3 downto 1);
				  CI <= C(2*widthDAT-3 downto widthDAT+1);CQ <= C(widthDAT-3 downto 1);
				  DI <= D(2*widthDAT-3 downto widthDAT+1);DQ <= D(widthDAT-3 downto 1);
	when "10" => AI <= A(2*widthDAT-2 downto widthDAT+2);AQ <= A(widthDAT-2 downto 2);
				  BI <= B(2*widthDAT-2 downto widthDAT+2);BQ <= B(widthDAT-2 downto 2);
				  CI <= C(2*widthDAT-2 downto widthDAT+2);CQ <= C(widthDAT-2 downto 2);
				  DI <= D(2*widthDAT-2 downto widthDAT+2);DQ <= D(widthDAT-2 downto 2);
	when "11" => AI <= A(2*widthDAT-1 downto widthDAT+3);AQ <= A(widthDAT-1 downto 3);
				  BI <= B(2*widthDAT-1 downto widthDAT+3);BQ <= B(widthDAT-1 downto 3);
				  CI <= C(2*widthDAT-1 downto widthDAT+3);CQ <= C(widthDAT-1 downto 3);
				  DI <= D(2*widthDAT-1 downto widthDAT+3);DQ <= D(widthDAT-1 downto 3);
	when others => null;
	end case;
	end process;
	
	process(AI,CI,AQ,CQ,BI,DI,BQ,DQ)
	begin
		S1 <= signed_addf (AI,CI); S2 <= signed_subf (AI,CI);
		S3 <= signed_addf (AQ,CQ); S4 <= signed_subf (AQ,CQ);
		S5 <= signed_addf (BI,DI); S6 <= signed_subf (BI,DI);
		S7 <= signed_addf (BQ,DQ); S8 <= signed_subf (BQ,DQ);
	end process ;
		
	process(clk)
	begin
	if clk'event and clk = '1' then
		if (enable0 = '1') then
			R1 <= signed_addf (S1,S5); R2 <= signed_addf (S3,S7);
			R3 <= signed_addf (S2,S8); R4 <= signed_subf (S4,S6);
			R5 <= signed_subf (S1,S5); R6 <= signed_subf (S3,S7);
			R7 <= signed_subf (S2,S8); R8 <= signed_addf (S4,S6);
		end if;
	end if;
	end process ;
	
	process(clk,cos1,sin1,cos2,sin2,cos3,sin3)
	begin
	if clk'event and clk = '1' then
		if (enable = '1') then
			cosw1 <= cos1; cosw2 <= cos2; cosw3 <= cos3; 
			sinw1 <= sin1; sinw2 <= sin2; sinw3 <= sin3; 
		end if;
	end if;
	end process ;
	 
	G3 <= GG3;G2 <= GG2;G1 <= GG1;G0 <= GG0;
	
	GG0 <= R1(R1'high)&R1 & R2(R2'high)&R2;
	
	g1_mult : ccmul 
    generic map (widthDAT =>widthDAT-1,widthRF =>widthRF)
    port map (
        clk  => clk,enable => enable1,
        cos => cosw1,sin => sinw1,
        Xre => R3,Xim => R4 , Y => GG1);
	
	g2_mult : ccmul 
    generic map (widthDAT =>widthDAT-1,widthRF =>widthRF)
    port map (
        clk  => clk,enable => enable1,
        cos => cosw2,sin => sinw2,
        Xre => R5,Xim => R6 , Y => GG2);
	
	g3_mult : ccmul 
    generic map (widthDAT =>widthDAT-1,widthRF =>widthRF)
    port map (
        clk => clk,enable => enable1,
        cos => cosw3,sin => sinw3,
        Xre => R7,Xim => R8 , Y => GG3);
	
	
	process(GG0,GG1,GG2,GG3)
	begin
	--if clk'event and clk = '1' then
		e1 <= '0' & (GG0(Bit2) xor GG0(Bit2-2))& (GG0(Bit2) xor GG0(Bit2-3));
		e2 <= '0' & (GG0(Bit) xor GG0(Bit-2))& (GG0(Bit) xor GG0(Bit-3));
		e3 <= (GG1(Bit2) xor GG1(Bit2-1)) & (GG1(Bit2) xor GG1(Bit2-2)) & (GG1(Bit2) xor GG1(Bit2-3));
		e4 <= (GG1(Bit) xor GG1(Bit-1)) & (GG1(Bit) xor GG1(Bit-2)) & (GG1(Bit) xor GG1(Bit-3));
		e5 <= (GG2(Bit2) xor GG2(Bit2-1)) & (GG2(Bit2) xor GG2(Bit2-2)) & (GG2(Bit2) xor GG2(Bit2-3));
		e6 <= (GG2(Bit) xor GG2(Bit-1)) & (GG2(Bit) xor GG2(Bit-2)) & (GG2(Bit) xor GG2(Bit-3));
		e7 <= (GG3(Bit2) xor GG3(Bit2-1)) & (GG3(Bit2) xor GG3(Bit2-2)) & (GG3(Bit2) xor GG3(Bit2-3));
		e8 <= (GG3(Bit) xor GG3(Bit-1)) & (GG3(Bit) xor GG3(Bit-2)) & (GG3(Bit) xor GG3(Bit-3));
	--end if;
	end process ;

	process(clk,expa,e1,e2,e3,e4,e5,e6,e7,e8)
	begin
	if clk'event and clk = '1' then
		expb <= Jexp (expa,e1,e2,e3,e4,e5,e6,e7,e8); -- 未测试
	end if;
	end process ;

end rtl;