📄 p18c658.inc
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DLC2 EQU H'0002'
DLC1 EQU H'0001'
DLC0 EQU H'0000'
;----- RXB0EIDL and RXB1EIDL Bits ----------------------------------------------------------
EID7 EQU H'0007'
EID6 EQU H'0006'
EID5 EQU H'0005'
EID4 EQU H'0004'
EID3 EQU H'0003'
EID2 EQU H'0002'
EID1 EQU H'0001'
EID0 EQU H'0000'
;----- RXB0EIDH, RXFnEIDH, and RXMnEIDH Bits ----------------------------------------------------------
EID15 EQU H'0007'
EID14 EQU H'0006'
EID13 EQU H'0005'
EID12 EQU H'0004'
EID11 EQU H'0003'
EID10 EQU H'0002'
EID9 EQU H'0001'
EID8 EQU H'0000'
;----- RXB0EIDL and TXB0EIDL Bits ----------------------------------------------------------
EID7 EQU H'0007'
EID6 EQU H'0006'
EID5 EQU H'0005'
EID4 EQU H'0004'
EID3 EQU H'0003'
EID2 EQU H'0002'
EID1 EQU H'0001'
EID0 EQU H'0000'
;----- RXB0SIDL, RXFnSIDL, and RXMnSIDL Bits ----------------------------------------------------------
SID2 EQU H'0007'
SID1 EQU H'0006'
SID0 EQU H'0005'
SRR EQU H'0004'
EXID EQU H'0003'
EID17 EQU H'0001'
EID16 EQU H'0000'
;----- RXB0SIDH, RXFnSIDH, RXMnSIDH Bits ----------------------------------------------------------
SID10 EQU H'0007'
SID9 EQU H'0006'
SID8 EQU H'0005'
SID7 EQU H'0004'
SID6 EQU H'0003'
SID5 EQU H'0002'
SID4 EQU H'0001'
SID3 EQU H'0001'
;----- RXB0CON Bits ----------------------------------------------------------
RXFUL EQU H'0007'
RXM1 EQU H'0006'
RXM0 EQU H'0005'
RXRTRRO EQU H'0003'
RX0DBEN EQU H'0002'
JTOFF EQU H'0001'
FILHIT0 EQU H'0000'
;----- RXB1CON Bits ----------------------------------------------------------
RXFUL EQU H'0007'
RXM1 EQU H'0006'
RXM0 EQU H'0005'
RXRTRRO EQU H'0003'
FILHIT2 EQU H'0002'
FILHIT1 EQU H'0001'
;----- TXB0CON Bits ----------------------------------------------------------
TXABT EQU H'0006'
TXLARB EQU H'0005'
TXERR EQU H'0004'
TXREQ EQU H'0003'
TXPRI1 EQU H'0001'
TXPRI0 EQU H'0000'
;----- TXBnSIDL Bits ----------------------------------------------------------
SID2 EQU H'0007'
SID1 EQU H'0006'
SID0 EQU H'0005'
EXIDE EQU H'0003'
EID17 EQU H'0001'
EID16 EQU H'0000'
;==========================================================================
;
; I/O Pin Name Definitions
;
;==========================================================================
;----- PORTA ------------------------------------------------------------------
RA0 EQU 0
AN0 EQU 0
RA1 EQU 1
AN1 EQU 1
RA2 EQU 2
AN2 EQU 2
VREFM EQU 2
RA3 EQU 3
AN3 EQU 3
VREFP EQU 3
RA4 EQU 4
T0CKI EQU 4
RA5 EQU 5
AN4 EQU 5
SS EQU 5
LVDIN EQU 5
RA6 EQU 6
OSC2 EQU 6
CLK0 EQU 6
;----- PORTB ------------------------------------------------------------------
RB0 EQU 0
INT0 EQU 0
RB1 EQU 1
INT1 EQU 1
RB2 EQU 2
INT2 EQU 2
RB3 EQU 3
INT3 EQU 3
RB4 EQU 4
RB5 EQU 5
RB6 EQU 6
RB7 EQU 7
;----- PORTC ------------------------------------------------------------------
RC0 EQU 0
T1OSO EQU 0
T1CKI EQU 0
RC1 EQU 1
T1OSI EQU 1
RC2 EQU 2
CCP1 EQU 2
RC3 EQU 3
SCK EQU 3
SCL EQU 3
RC4 EQU 4
SDI EQU 4
SDA EQU 4
RC5 EQU 5
SDO EQU 5
RC6 EQU 6
TX EQU 6
CK EQU 6
RC7 EQU 7
RX EQU 7
;****DT EQU 7 ;*** Not Available due to conflict with
;*** Define Table (DT) directive
;----- PORTD ------------------------------------------------------------------
RD0 EQU 0
PSP0 EQU 0
RD1 EQU 1
PSP1 EQU 1
RD2 EQU 2
PSP2 EQU 2
RD3 EQU 3
PSP3 EQU 3
RD4 EQU 4
PSP4 EQU 4
RD5 EQU 5
PSP5 EQU 5
RD6 EQU 6
PSP6 EQU 6
RD7 EQU 7
PSP7 EQU 7
;----- PORTE ------------------------------------------------------------------
RE0 EQU 0
ALE EQU 0
AN5 EQU 0
RE1 EQU 1
OE EQU 1
RE2 EQU 2
WRL EQU 2
RE3 EQU 3
WRH EQU 3
RE4 EQU 4
RE5 EQU 5
RE6 EQU 6
RE7 EQU 7
CCP2 EQU 7
;----- PORTF ------------------------------------------------------------------
RF0 EQU 0
AN5 EQU 0
RF1 EQU 1
AN6 EQU 1
RF2 EQU 2
AN7 EQU 2
RF3 EQU 3
AN8 EQU 3
RF4 EQU 4
AN9 EQU 4
RF5 EQU 5
AN10 EQU 5
RF6 EQU 6
AN11 EQU 6
RF7 EQU 7
;----- PORTG ------------------------------------------------------------------
RG0 EQU 0
CANTX1 EQU 0
RG1 EQU 1
CANTX2 EQU 1
RG2 EQU 2
CANRX EQU 2
RG3 EQU 3
RG4 EQU 4
;==========================================================================
;==========================================================================
;
; RAM Definition
;
;==========================================================================
; __MAXRAM H'5FF'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Code Protect:
; CP = ON Enabled
; CP = OFF Disabled
;
; Oscillator Selection:
; OSC = LP LP
; OSC = XT XT
; OSC = HS HS
; OSC = RC RC
; OSC = EC EC-OSC2 as Clock Out
; OSC = ECIO EC-OSC2 as RA6
; OSC = HSPLL HS-PLL Enabled
; OSC = RCIO RC-OSC2 as RA6
;
; Osc. Switch Enable:
; OSCS = ON Enabled
; OSCS = OFF Disabled
;
; Power-up Timer:
; PWRT = ON Enabled
; PWRT = OFF Disabled
;
; Brown-out Reset:
; BOR = OFF Disabled
; BOR = ON Enabled
;
; Brown-out Voltage:
; BORV = 45 4.5V
; BORV = 42 4.2V
; BORV = 27 2.7V
; BORV = 25 2.5V
;
; Watchdog Timer:
; WDT = OFF Disabled
; WDT = ON Enabled
;
; Watchdog Postscaler:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
;
; Stack Overflow Reset:
; STVR = OFF Disabled
; STVR = ON Enabled
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; Data Sheet Include File Address
; CONFIG1L = Configuration Byte 0 300000h
; CONFIG1H = Configuration Byte 1 300001h
; CONFIG2L = Configuration Byte 3 300002h
; CONFIG2H = Configuration Byte 4 300003h
; CONFIG3L = Configuration Byte 5 300004h
; CONFIG3H = Configuration Byte 6 300005h
; CONFIG4L = Configuration Byte 7 300006h
; CONFIG4H = Configuration Byte 8 300007h
;
;==========================================================================
;
;Configuration Byte 0 Options
_CP_ON_0 EQU H'00' ; Code Protect enable
_CP_OFF_0 EQU H'FF'
;Configuration Byte 1 Options
_OSCS_ON_1 EQU H'DF' ; Oscillator Switch enable
_OSCS_OFF_1 EQU H'FF'
_LP_OSC_1 EQU H'F8' ; Oscillator type
_XT_OSC_1 EQU H'F9'
_HS_OSC_1 EQU H'FA'
_RC_OSC_1 EQU H'FB'
_EC_OSC_1 EQU H'FC' ; External Clock w/OSC2 output divide by 4
_ECIO_OSC_1 EQU H'FD' ; w/OSC2 as an IO pin (RA6)
_HSPLL_OSC_1 EQU H'FE' ; HS PLL
_RCIO_OSC_1 EQU H'FF' ; RC w/OSC2 as an IO pin (RA6)
;Configuration Byte 2 Options
_BOR_ON_2 EQU H'FF' ; Brown-out Reset enable
_BOR_OFF_2 EQU H'FD'
_PWRT_OFF_2 EQU H'FF' ; Power-up Timer enable
_PWRT_ON_2 EQU H'FE'
_BORV_25_2 EQU H'FF' ; BOR Voltage - 2.5v
_BORV_27_2 EQU H'FB' ; 2.7v
_BORV_42_2 EQU H'F7' ; 4.2v
_BORV_45_2 EQU H'F3' ; 4.5v
;Configuration Byte 3 Options
_WDT_ON_3 EQU H'FF' ; Watch Dog Timer enable
_WDT_OFF_3 EQU H'FE'
_WDTPS_128_3 EQU H'FF' ; Watch Dog Timer PostScaler count
_WDTPS_64_3 EQU H'FD'
_WDTPS_32_3 EQU H'FB'
_WDTPS_16_3 EQU H'F9'
_WDTPS_8_3 EQU H'F7'
_WDTPS_4_3 EQU H'F5'
_WDTPS_2_3 EQU H'F3'
_WDTPS_1_3 EQU H'F1'
;Configuration Byte 6 Options
_STVR_ON_6 EQU H'FF' ; Stack over/underflow Reset enable
_STVR_OFF_6 EQU H'FE'
; To use the Configuration Bits, place the following lines in your source code
; in the following format, and change the configuration value to the desired
; setting (such as CP_OFF to CP_ON). These are currently commented out here
; and each __CONFIG line should have the preceding semicolon removed when
; pasted into your source code.
; The following is a assignment of address values for all of the configuration
; registers for the purpose of table reads
_CONFIG0 EQU H'300000'
_CONFIG1 EQU H'300001'
_CONFIG2 EQU H'300002'
_CONFIG3 EQU H'300003'
_CONFIG4 EQU H'300004'
_CONFIG5 EQU H'300005'
_CONFIG6 EQU H'300006'
_CONFIG7 EQU H'300007'
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
;Program Configuration Register 0
; __CONFIG _CONFIG0, _CP_OFF_0
;Program Configuration Register 1
; __CONFIG _CONFIG1, _OSCS_OFF_1 & _RCIO_OSC_1
;Program Configuration Register 2
; __CONFIG _CONFIG2, _BOR_ON_2 & _BORV_25_2 & _PWRT_OFF_2
;Program Configuration Register 3
; __CONFIG _CONFIG3, _WDT_ON_3 & _WDTPS_128_3
;Program Configuration Register 6
; __CONFIG _CONFIG6, _STVR_ON_6
;ID Locations Register 0
; __IDLOCS _IDLOC0, <expression>
;ID Locations Register 1
; __IDLOCS _IDLOC1, <expression>
;ID Locations Register 2
; __IDLOCS _IDLOC2, <expression>
;ID Locations Register 3
; __IDLOCS _IDLOC3, <expression>
;ID Locations Register 4
; __IDLOCS _IDLOC4, <expression>
;ID Locations Register 5
; __IDLOCS _IDLOC5, <expression>
;ID Locations Register 6
; __IDLOCS _IDLOC6, <expression>
;ID Locations Register 7
; __IDLOCS _IDLOC7, <expression>
;Device ID registers hold device ID and revision number and can only be read
;Device ID Register 1
; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0
;Device ID Register 2
; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3
;==========================================================================
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