📄 p18f4450.inc
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T0SE EQU H'0004'
T0CS EQU H'0005'
T08BIT EQU H'0006'
TMR0ON EQU H'0007'
;----- STATUS Bits -----------------------------------------------------
C EQU H'0000'
DC EQU H'0001'
Z EQU H'0002'
OV EQU H'0003'
N EQU H'0004'
;----- INTCON3 Bits -----------------------------------------------------
INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
INT1F EQU H'0000'
INT2F EQU H'0001'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT1P EQU H'0006'
INT2P EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
TMR0IP EQU H'0002'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
T0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
RBIE EQU H'0003'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0F EQU H'0001'
T0IF EQU H'0002'
INT0E EQU H'0004'
T0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKFUL EQU H'0007'
STKOVF EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0200'-H'03FF'
__BADRAM H'0500'-H'0F5F'
__BADRAM H'0F85'-H'0F88'
__BADRAM H'0F8E'-H'0F91'
__BADRAM H'0F97'-H'0F9C'
__BADRAM H'0FA3'-H'0FA5'
__BADRAM H'0FA8'-H'0FAA'
__BADRAM H'0FB1'-H'0FB7'
__BADRAM H'0FB9'-H'0FBC'
__BADRAM H'0FC5'-H'0FC9'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; 96 MHz PLL Prescaler:
; PLLDIV = 1 No divide (4 MHz input)
; PLLDIV = 2 Divide by 2 (8 MHz input)
; PLLDIV = 3 Divide by 3 (12 MHz input)
; PLLDIV = 4 Divide by 4 (16 MHz input)
; PLLDIV = 5 Divide by 5 (20 MHz input)
; PLLDIV = 6 Divide by 6 (24 MHz input)
; PLLDIV = 10 Divide by 10 (40 MHz input)
; PLLDIV = 12 Divide by 12 (48 MHz input)
;
; CPU System Clock Postscaler:
; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
;
; Full-Speed USB Clock Source Selection:
; USBDIV = 1 Clock source from OSC1/OSC2
; USBDIV = 2 Clock source from 96 MHz PLL/2
;
; Oscillator Selection bits:
; FOSC = XT_XT XT oscillator, XT used by USB
; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB
; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
; FOSC = INTOSC_XT Internal oscillator, XT used by USB
; FOSC = INTOSC_HS Internal oscillator, HS used by USB
; FOSC = HS HS oscillator, HS used by USB
; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
;
; Fail-Safe Clock Monitor:
; FCMEN = OFF Disabled
; FCMEN = ON Enabled
;
; Internal/External Switch Over:
; IESO = OFF Disabled
; IESO = ON Enabled
;
; Power-up Timer:
; PWRT = ON Enabled
; PWRT = OFF Disabled
;
; Brown-out Reset:
; BOR = OFF Disabled
; BOR = SOFT Controlled by SBOREN
; BOR = ON_ACTIVE Enabled when the device is not in Sleep, SBOREN bit is disabled
; BOR = ON Enabled, SBOREN bit is disabled
;
; Brown-out Voltage:
; BORV = 46 4.6V
; BORV = 43 4.3V
; BORV = 28 2.8V
; BORV = 21 2.1V
;
; USB Voltage Regulator Enable:
; VREGEN = OFF Disabled
; VREGEN = ON Enabled
;
; Watchdog Timer:
; WDT = OFF HW Disabled - SW Controlled
; WDT = ON HW Enabled - SW Disabled
;
; Watchdog Postscaler:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; MCLR Enable:
; MCLRE = OFF Disabled
; MCLRE = ON Enabled
;
; Low Power Timer1 Oscillator Enable:
; LPT1OSC = OFF Timer1 oscillator configured for high power
; LPT1OSC = ON Timer1 oscillator configured for low power
;
; PORTB A/D Enable:
; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset
; PBADEN = ON PORTB<4:0> pins are configured as analog input on Reset
;
; Stack Overflow Reset:
; STVREN = OFF Disabled
; STVREN = ON Enabled
;
; Low Voltage ICSP:
; LVP = OFF Disabled
; LVP = ON Enabled
;
; Boot Block Size Select Bit:
; BBSIZ = BB1K 1KW Boot Block Size
; BBSIZ = BB2K 2KW Boot Block Size
;
; Dedicated In-Circuit Debug/Programming Enable:
; ICPRT = OFF Disabled
; ICPRT = ON Enabled
;
; Extended Instruction Set Enable:
; XINST = OFF Disabled
; XINST = ON Enabled
;
; Background Debugger Enable:
; DEBUG = ON Enabled
; DEBUG = OFF Disabled
;
; Code Protection Block 0:
; CP0 = ON Enabled
; CP0 = OFF Disabled
;
; Code Protection Block 1:
; CP1 = ON Enabled
; CP1 = OFF Disabled
;
; Boot Block Code Protection:
; CPB = ON Enabled
; CPB = OFF Disabled
;
; Write Protection Block 0:
; WRT0 = ON Enabled
; WRT0 = OFF Disabled
;
; Write Protection Block 1:
; WRT1 = ON Enabled
; WRT1 = OFF Disabled
;
; Boot Block Write Protection:
; WRTB = ON Enabled
; WRTB = OFF Disabled
;
; Configuration Register Write Protection:
; WRTC = ON Enabled
; WRTC = OFF Disabled
;
; Table Read Protection Block 0:
; EBTR0 = ON Enabled
; EBTR0 = OFF Disabled
;
; Table Read Protection Block 1:
; EBTR1 = ON Enabled
; EBTR1 = OFF Disabled
;
; Boot Block Table Read Protection:
; EBTRB = ON Enabled
; EBTRB = OFF Disabled
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1L 300000h
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
; CONFIG5H 300009h
; CONFIG6L 30000Ah
; CONFIG6H 30000Bh
; CONFIG7L 30000Ch
; CONFIG7H 30000Dh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1L EQU H'300000'
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1L Options --------------------------------------------------
_PLLDIV_1_1L EQU H'F8' ; No divide (4 MHz input)
_PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz input)
_PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz input)
_PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz input)
_PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz input)
_PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz input)
_PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz input)
_PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz input)
_CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
_CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
_CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
_CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
_USBDIV_1_1L EQU H'DF' ; Clock source from OSC1/OSC2
_USBDIV_2_1L EQU H'FF' ; Clock source from 96 MHz PLL/2
;----- CONFIG1H Options --------------------------------------------------
_FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB
_FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB
_FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB
_FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB
_FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB
_FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB
_FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB
_FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB
_FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB
_FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB
_FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB
_FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB
_FCMEN_OFF_1H EQU H'BF' ; Disabled
_FCMEN_ON_1H EQU H'FF' ; Enabled
_IESO_OFF_1H EQU H'7F' ; Disabled
_IESO_ON_1H EQU H'FF' ; Enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; Enabled
_PWRT_OFF_2L EQU H'FF' ; Disabled
_BOR_OFF_2L EQU H'F9' ; Disabled
_BOR_SOFT_2L EQU H'FB' ; Controlled by SBOREN
_BOR_ON_ACTIVE_2L EQU H'FD' ; Enabled when the device is not in Sleep, SBOREN bit is disabled
_BOR_ON_2L EQU H'FF' ; Enabled, SBOREN bit is disabled
_BORV_46_2L EQU H'E7' ; 4.6V
_BORV_43_2L EQU H'EF' ; 4.3V
_BORV_28_2L EQU H'F7' ; 2.8V
_BORV_21_2L EQU H'FF' ; 2.1V
_VREGEN_OFF_2L EQU H'DF' ; Disabled
_VREGEN_ON_2L EQU H'FF' ; Enabled
;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled
_WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3H Options --------------------------------------------------
_MCLRE_OFF_3H EQU H'7F' ; Disabled
_MCLRE_ON_3H EQU H'FF' ; Enabled
_LPT1OSC_OFF_3H EQU H'FB' ; Timer1 oscillator configured for high power
_LPT1OSC_ON_3H EQU H'FF' ; Timer1 oscillator configured for low power
_PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset
_PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input on Reset
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Disabled
_STVREN_ON_4L EQU H'FF' ; Enabled
_LVP_OFF_4L EQU H'FB' ; Disabled
_LVP_ON_4L EQU H'FF' ; Enabled
_BBSIZ_BB1K_4L EQU H'F7' ; 1KW Boot Block Size
_BBSIZ_BB2K_4L EQU H'FF' ; 2KW Boot Block Size
_ICPRT_OFF_4L EQU H'DF' ; Disabled
_ICPRT_ON_4L EQU H'FF' ; Enabled
_XINST_OFF_4L EQU H'BF' ; Disabled
_XINST_ON_4L EQU H'FF' ; Enabled
_DEBUG_ON_4L EQU H'7F' ; Enabled
_DEBUG_OFF_4L EQU H'FF' ; Disabled
;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE' ; Enabled
_CP0_OFF_5L EQU H'FF' ; Disabled
_CP1_ON_5L EQU H'FD' ; Enabled
_CP1_OFF_5L EQU H'FF' ; Disabled
;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF' ; Enabled
_CPB_OFF_5H EQU H'FF' ; Disabled
;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE' ; Enabled
_WRT0_OFF_6L EQU H'FF' ; Disabled
_WRT1_ON_6L EQU H'FD' ; Enabled
_WRT1_OFF_6L EQU H'FF' ; Disabled
;----- CONFIG6H Options --------------------------------------------------
_WRTB_ON_6H EQU H'BF' ; Enabled
_WRTB_OFF_6H EQU H'FF' ; Disabled
_WRTC_ON_6H EQU H'DF' ; Enabled
_WRTC_OFF_6H EQU H'FF' ; Disabled
;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE' ; Enabled
_EBTR0_OFF_7L EQU H'FF' ; Disabled
_EBTR1_ON_7L EQU H'FD' ; Enabled
_EBTR1_OFF_7L EQU H'FF' ; Disabled
;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF' ; Enabled
_EBTRB_OFF_7H EQU H'FF' ; Disabled
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
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