📄 p18f448.inc
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TXB0D00 EQU H'0000'
;==========================================================================
;
; I/O Pin Name Definitions
;
;==========================================================================
;----- PORTA ------------------------------------------------------------------
RA0 EQU 0
AN0 EQU 0
CVREF EQU 0
RA1 EQU 1
AN1 EQU 1
RA2 EQU 2
AN2 EQU 2
VREFM EQU 2
RA3 EQU 3
AN3 EQU 3
VREFP EQU 3
RA4 EQU 4
T0CKI EQU 4
RA5 EQU 5
AN4 EQU 5
SS EQU 5
NOT_SS EQU 5
LVDIN EQU 5
RA6 EQU 6
OSC2 EQU 6
CLKO EQU 6
;----- PORTB ------------------------------------------------------------------
RB0 EQU 0
INT0 EQU 0
RB1 EQU 1
INT1 EQU 1
RB2 EQU 2
CANTX EQU 2
RB3 EQU 3
CANRX EQU 3
RB4 EQU 4
RB5 EQU 5
PGM EQU 5
RB6 EQU 6
PGC EQU 6
RB7 EQU 7
PGD EQU 7
;----- PORTC ------------------------------------------------------------------
RC0 EQU 0
T1OSO EQU 0
T1CKI EQU 0
RC1 EQU 1
T1OSI EQU 1
RC2 EQU 2
CCP1 EQU 2
RC3 EQU 3
SCK EQU 3
SCL EQU 3
RC4 EQU 4
SDI EQU 4
SDA EQU 4
RC5 EQU 5
SDO EQU 5
RC6 EQU 6
TX EQU 6
CK EQU 6
RC7 EQU 7
RX EQU 7
;****DT EQU 7 ;*** Not Available due to conflict with
;*** Define Table (DT) directive
;----- PORTD ------------------------------------------------------------------
RD0 EQU 0
PSP0 EQU 0
C1INP EQU 0
RD1 EQU 1
PSP1 EQU 1
C1INM EQU 1
RD2 EQU 2
PSP2 EQU 2
C2INP EQU 2
RD3 EQU 3
PSP3 EQU 3
C2INM EQU 3
RD4 EQU 4
PSP4 EQU 4
ECCP1 EQU 4
P1A EQU 4
RD5 EQU 5
PSP5 EQU 5
P1B EQU 5
RD6 EQU 6
PSP6 EQU 6
P1C EQU 6
RD7 EQU 7
PSP7 EQU 7
P1D EQU 7
;----- PORTE ------------------------------------------------------------------
RE0 EQU 0
RD EQU 0
NOT_RD EQU 0
AN5 EQU 0
RE1 EQU 1
;WR EQU 1 *** Already defined by EECON.WR, also bit 1
NOT_WR EQU 1
AN6 EQU 1
RE2 EQU 2
CS EQU 2
NOT_CS EQU 2
AN7 EQU 2
;==========================================================================
;
; RAM Definition
;
;==========================================================================
__MAXRAM H'FFF'
__BADRAM H'300'-H'EFF'
__BADRAM H'FD4',H'FC0',H'FB9',H'FB8',H'FAA',H'F97'-H'F9C'
__BADRAM H'F8E'-H'F91',H'F85'-H'F88', H'F79'-H'F7F',H'F77'
__BADRAM H'F5F',H'F4F',H'F3F',H'F2F'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Oscillator Selection:
; OSC = LP LP
; OSC = XT XT
; OSC = HS HS
; OSC = RC RC
; OSC = EC EC-OSC2 as Clock Out
; OSC = ECIO EC-OSC2 as RA6
; OSC = HSPLL HS-PLL Enabled
; OSC = RCIO RC-OSC2 as RA6
;
; Osc. Switch Enable:
; OSCS = ON Enabled
; OSCS = OFF Disabled
;
; Power-up Timer:
; PWRT = ON Enabled
; PWRT = OFF Disabled
;
; Brown-out Reset:
; BOR = OFF Disabled
; BOR = ON Enabled
;
; Brown-out Voltage:
; BORV = 45 4.5V
; BORV = 42 4.2V
; BORV = 27 2.7V
; BORV = 20 2.0V
;
; Watchdog Timer:
; WDT = OFF Disabled
; WDT = ON Enabled
;
; Watchdog Postscaler:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
;
; Stack Overflow Reset:
; STVR = OFF Disabled
; STVR = ON Enabled
;
; Low Voltage ICSP:
; LVP = OFF Disabled
; LVP = ON Enabled
;
; Background Debugger Enable:
; DEBUG = ON Enabled
; DEBUG = OFF Disabled
;
; Code Protection Block 0:
; CP0 = ON Enabled
; CP0 = OFF Disabled
;
; Code Protection Block 1:
; CP1 = ON Enabled
; CP1 = OFF Disabled
;
; Boot Block Code Protection:
; CPB = ON Enabled
; CPB = OFF Disabled
;
; Data EEPROM Code Protection:
; CPD = ON Enabled
; CPD = OFF Disabled
;
; Write Protection Block 0:
; WRT0 = ON Enabled
; WRT0 = OFF Disabled
;
; Write Protection Block 1:
; WRT1 = ON Enabled
; WRT1 = OFF Disabled
;
; Boot Block Write Protection:
; WRTB = ON Enabled
; WRTB = OFF Disabled
;
; Configuration Register Write Protection:
; WRTC = ON Enabled
; WRTC = OFF Disabled
;
; Data EEPROM Write Protection:
; WRTD = ON Enabled
; WRTD = OFF Disabled
;
; Table Read Protection Block 0:
; EBTR0 = ON Enabled
; EBTR0 = OFF Disabled
;
; Table Read Protection Block 1:
; EBTR1 = ON Enabled
; EBTR1 = OFF Disabled
;
; Boot Block Table Read Protection:
; EBTRB = ON Enabled
; EBTRB = OFF Disabled
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; Data Sheet Include File Address
; CONFIG1H = Configuration Byte 1H 300001h
; CONFIG2L = Configuration Byte 2L 300002h
; CONFIG2H = Configuration Byte 2H 300003h
; CONFIG4L = Configuration Byte 4L 300006h
; CONFIG5L = Configuration Byte 5L 300008h
; CONFIG5H = Configuration Byte 5H 300009h
; CONFIG6L = Configuration Byte 6L 30000Ah
; CONFIG6H = Configuration Byte 6H 30000Bh
; CONFIG7L = Configuration Byte 7L 30000Ch
; CONFIG7H = Configuration Byte 7H 30000Dh
;
;==========================================================================
;Configuration Byte 1H Options
_OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable
_OSCS_OFF_1H EQU H'FF'
_LP_OSC_1H EQU H'F8' ; Oscillator type
_XT_OSC_1H EQU H'F9'
_HS_OSC_1H EQU H'FA'
_RC_OSC_1H EQU H'FB'
_EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4
_ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6)
_HSPLL_OSC_1H EQU H'FE' ; HS PLL
_RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6)
;Configuration Byte 2L Options
_BOR_ON_2L EQU H'FF' ; Brown-out Reset enable
_BOR_OFF_2L EQU H'FD'
_PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable
_PWRT_ON_2L EQU H'FE'
_BORV_25_2L EQU H'FF' ; BOR Voltage - 2.5v
_BORV_27_2L EQU H'FB' ; 2.7v
_BORV_42_2L EQU H'F7' ; 4.2v
_BORV_45_2L EQU H'F3' ; 4.5v
;Configuration Byte 2H Options
_WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable
_WDT_OFF_2H EQU H'FE'
_WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count
_WDTPS_64_2H EQU H'FD'
_WDTPS_32_2H EQU H'FB'
_WDTPS_16_2H EQU H'F9'
_WDTPS_8_2H EQU H'F7'
_WDTPS_4_2H EQU H'F5'
_WDTPS_2_2H EQU H'F3'
_WDTPS_1_2H EQU H'F1'
;Configuration Byte 4L Options
_DEBUG_ON_4L EQU H'7F' ; Enabled
_DEBUG_OFF_4L EQU H'FF' ; Disabled
_LVP_ON_4L EQU H'FF' ; Enabled
_LVP_OFF_4L EQU H'FB' ; Disabled
_STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable
_STVR_OFF_4L EQU H'FE'
;Configuration Byte 5L Options
_CP0_ON_5L EQU H'FE' ; Enabled
_CP0_OFF_5L EQU H'FF' ; Disabled
_CP1_ON_5L EQU H'FD' ; Enabled
_CP1_OFF_5L EQU H'FF' ; Disabled
;Configuration Byte 5H Options
_CPB_ON_5H EQU H'BF' ; Enabled
_CPB_OFF_5H EQU H'FF' ; Disabled
_CPD_ON_5H EQU H'7F' ; Enabled
_CPD_OFF_5H EQU H'FF' ; Disabled
;Configuration Byte 6L Options
_WRT0_ON_6L EQU H'FE' ; Enabled
_WRT0_OFF_6L EQU H'FF' ; Disabled
_WRT1_ON_6L EQU H'FD' ; Enabled
_WRT1_OFF_6L EQU H'FF' ; Disabled
;Configuration Byte 6H Options
_WRTB_ON_6H EQU H'BF' ; Enabled
_WRTB_OFF_6H EQU H'FF' ; Disabled
_WRTC_ON_6H EQU H'DF' ; Enabled
_WRTC_OFF_6H EQU H'FF' ; Disabled
_WRTD_ON_6H EQU H'7F' ; Enabled
_WRTD_OFF_6H EQU H'FF' ; Disabled
;Configuration Byte 7L Options
_EBTR0_ON_7L EQU H'FE' ; Enabled
_EBTR0_OFF_7L EQU H'FF' ; Disabled
_EBTR1_ON_7L EQU H'FD' ; Enabled
_EBTR1_OFF_7L EQU H'FF' ; Disabled
;Configuration Byte 7H Options
_EBTRB_ON_7H EQU H'BF' ; Enabled
_EBTRB_OFF_7H EQU H'FF' ; Disabled
; To use the Configuration Bits, place the following lines in your source code
; in the following format, and change the configuration value to the desired
; setting (such as _BOR_ON_2L). These are currently commented out here
; and each __CONFIG line should have the preceding semicolon removed when
; pasted into your source code.
; The following is a assignment of address values for all of the configuration
; registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
;Program Configuration Register 1H
; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H
;Program Configuration Register 2L
; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_25_2L & _PWRT_OFF_2L
;Program Configuration Register 2H
; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H
;Program Configuration Register 4L
; __CONFIG _CONFIG4L, _STVR_ON_4L
;ID Locations Register 0
; __IDLOCS _IDLOC0, <expression>
;ID Locations Register 1
; __IDLOCS _IDLOC1, <expression>
;ID Locations Register 2
; __IDLOCS _IDLOC2, <expression>
;ID Locations Register 3
; __IDLOCS _IDLOC3, <expression>
;ID Locations Register 4
; __IDLOCS _IDLOC4, <expression>
;ID Locations Register 5
; __IDLOCS _IDLOC5, <expression>
;ID Locations Register 6
; __IDLOCS _IDLOC6, <expression>
;ID Locations Register 7
; __IDLOCS _IDLOC7, <expression>
;Device ID registers hold device ID and revision number and can only be read
;Device ID Register 1
; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0
;Device ID Register 2
; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3
;==========================================================================
LIST
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