📄 p18f8520.inc
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INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT3IF EQU H'0002'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT3IE EQU H'0005'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
INT1F EQU H'0000'
INT2F EQU H'0001'
INT3F EQU H'0002'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT3E EQU H'0005'
INT1P EQU H'0006'
INT2P EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
INT3IP EQU H'0001'
TMR0IP EQU H'0002'
INTEDG3 EQU H'0003'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
INT3P EQU H'0001'
T0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
RBIE EQU H'0003'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0F EQU H'0001'
T0IF EQU H'0002'
INT0E EQU H'0004'
T0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKOVF EQU H'0007'
STKFUL EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0800'-H'0F5F'
__BADRAM H'0F79'-H'0F7F'
__BADRAM H'0F9B'
__BADRAM H'0FB6'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Oscillator Selection:
; OSC = LP LP
; OSC = XT XT
; OSC = HS HS
; OSC = RC RC-OSC2 as Clock Out
; OSC = EC EC-OSC2 as Clock Out
; OSC = ECIO EC-OSC2 as RA6
; OSC = HSPLL HS-PLL Enabled
; OSC = RCIO RC-OSC2 as RA6
;
; Osc. Switch Enable:
; OSCS = ON Enabled
; OSCS = OFF Disabled
;
; Power-up Timer:
; PWRT = ON Enabled
; PWRT = OFF Disabled
;
; Brown-out Reset:
; BOR = OFF Disabled
; BOR = ON Enabled
;
; Brown-out Voltage:
; BORV = 45 4.5V
; BORV = 42 4.2V
; BORV = 27 2.7V
; BORV = 25 2.5V
;
; Watchdog Timer:
; WDT = OFF Disabled
; WDT = ON Enabled
;
; Watchdog Postscaler:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
;
; Processor Mode Selection:
; MODE = EM Extended Microcontroller mode
; MODE = MPB Microprocessor with Boot Block mode
; MODE = MP Microprocessor mode
; MODE = MC Microcontroller mode
;
; External Bus Data Wait:
; WAIT = ON Enabled
; WAIT = OFF Disabled
;
; CCP2 MUX:
; CCP2MUX = OFF Uses RE7
; CCP2MUX = RE7 Uses RE7
; CCP2MUX = ON Uses RC1
; CCP2MUX = RC1 Uses RC1
;
; Stack Overflow Reset:
; STVR = OFF Disabled
; STVR = ON Enabled
;
; Low Voltage ICSP:
; LVP = OFF Disabled
; LVP = ON Enabled
;
; Background Debugger Enable:
; DEBUG = ON Enabled
; DEBUG = OFF Disabled
;
; Code Protection Block 0:
; CP0 = ON Enabled
; CP0 = OFF Disabled
;
; Code Protection Block 1:
; CP1 = ON Enabled
; CP1 = OFF Disabled
;
; Code Protection Block 2:
; CP2 = ON Enabled
; CP2 = OFF Disabled
;
; Code Protection Block 3:
; CP3 = ON Enabled
; CP3 = OFF Disabled
;
; Boot Block Code Protection:
; CPB = ON Enabled
; CPB = OFF Disabled
;
; Data EEPROM Code Protection:
; CPD = ON Enabled
; CPD = OFF Disabled
;
; Write Protection Block 0:
; WRT0 = ON Enabled
; WRT0 = OFF Disabled
;
; Write Protection Block 1:
; WRT1 = ON Enabled
; WRT1 = OFF Disabled
;
; Write Protection Block 2:
; WRT2 = ON Enabled
; WRT2 = OFF Disabled
;
; Write Protection Block 3:
; WRT3 = ON Enabled
; WRT3 = OFF Disabled
;
; Boot Block Write Protection:
; WRTB = ON Enabled
; WRTB = OFF Disabled
;
; Configuration Register Write Protection:
; WRTC = ON Enabled
; WRTC = OFF Disabled
;
; Data EEPROM Write Protection:
; WRTD = ON Enabled
; WRTD = OFF Disabled
;
; Table Read Protection Block 0:
; EBTR0 = ON Enabled
; EBTR0 = OFF Disabled
;
; Table Read Protection Block 1:
; EBTR1 = ON Enabled
; EBTR1 = OFF Disabled
;
; Table Read Protection Block 2:
; EBTR2 = ON Enabled
; EBTR2 = OFF Disabled
;
; Table Read Protection Block 3:
; EBTR3 = ON Enabled
; EBTR3 = OFF Disabled
;
; Boot Block Table Read Protection:
; EBTRB = ON Enabled
; EBTRB = OFF Disabled
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3L 300004h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
; CONFIG5H 300009h
; CONFIG6L 30000Ah
; CONFIG6H 30000Bh
; CONFIG7L 30000Ch
; CONFIG7H 30000Dh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3L EQU H'300004'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1H Options --------------------------------------------------
_OSC_LP_1H EQU H'F8' ; LP
_OSC_XT_1H EQU H'F9' ; XT
_OSC_HS_1H EQU H'FA' ; HS
_OSC_RC_1H EQU H'FB' ; RC-OSC2 as Clock Out
_OSC_EC_1H EQU H'FC' ; EC-OSC2 as Clock Out
_OSC_ECIO_1H EQU H'FD' ; EC-OSC2 as RA6
_OSC_HSPLL_1H EQU H'FE' ; HS-PLL Enabled
_OSC_RCIO_1H EQU H'FF' ; RC-OSC2 as RA6
_OSCS_ON_1H EQU H'DF' ; Enabled
_OSCS_OFF_1H EQU H'FF' ; Disabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; Enabled
_PWRT_OFF_2L EQU H'FF' ; Disabled
_BOR_OFF_2L EQU H'FD' ; Disabled
_BOR_ON_2L EQU H'FF' ; Enabled
_BORV_45_2L EQU H'F3' ; 4.5V
_BORV_42_2L EQU H'F7' ; 4.2V
_BORV_27_2L EQU H'FB' ; 2.7V
_BORV_25_2L EQU H'FF' ; 2.5V
;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H EQU H'FE' ; Disabled
_WDT_ON_2H EQU H'FF' ; Enabled
_WDTPS_1_2H EQU H'F1' ; 1:1
_WDTPS_2_2H EQU H'F3' ; 1:2
_WDTPS_4_2H EQU H'F5' ; 1:4
_WDTPS_8_2H EQU H'F7' ; 1:8
_WDTPS_16_2H EQU H'F9' ; 1:16
_WDTPS_32_2H EQU H'FB' ; 1:32
_WDTPS_64_2H EQU H'FD' ; 1:64
_WDTPS_128_2H EQU H'FF' ; 1:128
;----- CONFIG3L Options --------------------------------------------------
_MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode
_MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode
_MODE_MP_3L EQU H'FE' ; Microprocessor mode
_MODE_MC_3L EQU H'FF' ; Microcontroller mode
_WAIT_ON_3L EQU H'7F' ; Enabled
_WAIT_OFF_3L EQU H'FF' ; Disabled
;----- CONFIG3H Options --------------------------------------------------
_CCP2MUX_OFF_3H EQU H'FE' ; Uses RE7
_CCP2MUX_RE7_3H EQU H'FE' ; Uses RE7
_CCP2MUX_ON_3H EQU H'FF' ; Uses RC1
_CCP2MUX_RC1_3H EQU H'FF' ; Uses RC1
;----- CONFIG4L Options --------------------------------------------------
_STVR_OFF_4L EQU H'FE' ; Disabled
_STVR_ON_4L EQU H'FF' ; Enabled
_LVP_OFF_4L EQU H'FB' ; Disabled
_LVP_ON_4L EQU H'FF' ; Enabled
_DEBUG_ON_4L EQU H'7F' ; Enabled
_DEBUG_OFF_4L EQU H'FF' ; Disabled
;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE' ; Enabled
_CP0_OFF_5L EQU H'FF' ; Disabled
_CP1_ON_5L EQU H'FD' ; Enabled
_CP1_OFF_5L EQU H'FF' ; Disabled
_CP2_ON_5L EQU H'FB' ; Enabled
_CP2_OFF_5L EQU H'FF' ; Disabled
_CP3_ON_5L EQU H'F7' ; Enabled
_CP3_OFF_5L EQU H'FF' ; Disabled
;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF' ; Enabled
_CPB_OFF_5H EQU H'FF' ; Disabled
_CPD_ON_5H EQU H'7F' ; Enabled
_CPD_OFF_5H EQU H'FF' ; Disabled
;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE' ; Enabled
_WRT0_OFF_6L EQU H'FF' ; Disabled
_WRT1_ON_6L EQU H'FD' ; Enabled
_WRT1_OFF_6L EQU H'FF' ; Disabled
_WRT2_ON_6L EQU H'FB' ; Enabled
_WRT2_OFF_6L EQU H'FF' ; Disabled
_WRT3_ON_6L EQU H'F7' ; Enabled
_WRT3_OFF_6L EQU H'FF' ; Disabled
;----- CONFIG6H Options --------------------------------------------------
_WRTB_ON_6H EQU H'BF' ; Enabled
_WRTB_OFF_6H EQU H'FF' ; Disabled
_WRTC_ON_6H EQU H'DF' ; Enabled
_WRTC_OFF_6H EQU H'FF' ; Disabled
_WRTD_ON_6H EQU H'7F' ; Enabled
_WRTD_OFF_6H EQU H'FF' ; Disabled
;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE' ; Enabled
_EBTR0_OFF_7L EQU H'FF' ; Disabled
_EBTR1_ON_7L EQU H'FD' ; Enabled
_EBTR1_OFF_7L EQU H'FF' ; Disabled
_EBTR2_ON_7L EQU H'FB' ; Enabled
_EBTR2_OFF_7L EQU H'FF' ; Disabled
_EBTR3_ON_7L EQU H'F7' ; Enabled
_EBTR3_OFF_7L EQU H'FF' ; Disabled
;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF' ; Enabled
_EBTRB_OFF_7H EQU H'FF' ; Disabled
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
LIST
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