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RCEN EQU H'0003'
PEN EQU H'0002'
RSEN EQU H'0001'
SEN EQU H'0000'
;----- ADCON0 Bits -----------------------------------------------------
GO EQU H'0001'
NOT_DONE EQU H'0001'
DONE EQU H'0001'
GO_DONE EQU H'0001'
ADON EQU H'0000'
;----- ADCON1 Bits -----------------------------------------------------
ADCOV EQU H'0007'
SIZE2 EQU H'0006'
SIZE1 EQU H'0005'
SIZE0 EQU H'0004'
BALC4 EQU H'0003'
BALC3 EQU H'0002'
BALC2 EQU H'0001'
BALC1 EQU H'0000'
;----- ADCON2 Bits -----------------------------------------------------
C340 EQU H'0007'
ADCS3 EQU H'0003'
ADCS2 EQU H'0002'
ADCS1 EQU H'0001'
ADCS0 EQU H'0000'
;----- CVRCON Bits -----------------------------------------------------
CWI4 EQU H'0007'
CWI3 EQU H'0006'
CWI2 EQU H'0005'
CWI1 EQU H'0004'
CWI0 EQU H'0003'
CWV2 EQU H'0002'
CWV1 EQU H'0001'
CWV0 EQU H'0000'
;----- CMCON bits ------------------------------------------------------
CWTST EQU H'0007'
CWVI EQU H'0004'
CWCI EQU H'0003'
CWDI EQU H'0002'
CWIEN EQU H'0001'
CWVEN EQU H'0000'
;----- T3CON Bits ------------------------------------------------------
RD16 EQU H'0007'
T3CCP2 EQU H'0006'
T3CKPS1 EQU H'0005'
T3CKPS0 EQU H'0004'
T3CCP1 EQU H'0003'
NOT_T3SYNC EQU H'0002'
T3SYNC EQU H'0002'
T3INSYNC EQU H'0002' ; Backward compatibility only
TMR3CS EQU H'0001'
TMR3ON EQU H'0000'
;----- EECON1 Bits -----------------------------------------------------
EEPGD EQU H'0007'
CFGS EQU H'0006'
COMA EQU H'0005'
FREE EQU H'0004'
WRERR EQU H'0003'
WREN EQU H'0002'
WR EQU H'0001'
RD EQU H'0000'
;----- IPR2 Bits -------------------------------------------------------
CMIP EQU H'0006'
EEIP EQU H'0004'
BCLIP EQU H'0003'
TMR3IP EQU H'0001'
;----- PIR2 Bits -------------------------------------------------------
CMIF EQU H'0006'
EEIF EQU H'0004'
BCLIF EQU H'0003'
TMR3IF EQU H'0001'
;----- PIE2 Bits -------------------------------------------------------
CMIE EQU H'0006'
EEIE EQU H'0004'
BCLIE EQU H'0003'
TMR3IE EQU H'0001'
;----- IPR1 Bits -------------------------------------------------------
ADIP EQU H'0006'
SSPIP EQU H'0003'
TMR2IP EQU H'0001'
TMR1IP EQU H'0000'
;----- PIR1 Bits -------------------------------------------------------
ADIF EQU H'0006'
SSPIF EQU H'0003'
TMR2IF EQU H'0001'
TMR1IF EQU H'0000'
;----- PIE1 Bits -------------------------------------------------------
ADIE EQU H'0006'
SSPIE EQU H'0003'
TMR2IE EQU H'0001'
TMR1IE EQU H'0000'
;----- BGCAL Bits -------------------------------------------------------
BGTC3 EQU H'0003'
BGTC2 EQU H'0002'
BGTC1 EQU H'0001'
BGTC0 EQU H'0000'
;----- OSCCAL Bits ----------------------------------------------------
REXT EQU H'0007'
OSC6 EQU H'0006'
OSC5 EQU H'0005'
OSC4 EQU H'0004'
OSC3 EQU H'0003'
OSC2 EQU H'0002'
OSC1 EQU H'0001'
OSC0 EQU H'0000'
;----- LEDDC Bits -------------------------------------------------------
LEDC2 EQU H'0002'
LEDC1 EQU H'0001'
LEDC0 EQU H'0000'
;----- WDTCON Bits -------------------------------------------------------
SWDTEN EQU H'0000'
;=======================================================================
;
; I/O Pin Name Definitions
;
;=======================================================================
;----- PORTA -----------------------------------------------------------
RA0 EQU 0
SCK EQU 0
SCL EQU 0
RA1 EQU 1
SDI EQU 1
SDA EQU 1
RA2 EQU 2
SS EQU 2
RA3 EQU 3
SDO EQU 3
RA4 EQU 4
T0CKI EQU 4
RA5 EQU 5
MCLR EQU 5
RA6 EQU 6
CLKI EQU 6
;----- PORTB -----------------------------------------------------------
RB0 EQU 0
INT0 EQU 0
RB1 EQU 1
INT1 EQU 1
RB2 EQU 2
INT2 EQU 2
RB3 EQU 3
RB4 EQU 4
RB5 EQU 5
RB6 EQU 6
PGC EQU 6
P1C EQU 7
RB7 EQU 7
PGD EQU 7
;=======================================================================
;
; RAM Definition
;
;=======================================================================
__MAXRAM H'FFF'
__BADRAM H'200'-H'F7F'
__BADRAM H'F82'-H'F88',H'F8B'-H'F8F',H'F94'-H'F99'
__BADRAM H'FA3'-H'FA5',H'FAA'-H'FB0',H'FB6'-H'FBF'
__BADRAM H'FD1'-H'FD2'
;=======================================================================
;
; ID Location Registers
;
; The following is an assignment of address values for all of the
; ID Location registers for the purpose of table reads and writes,
; and for device programming.
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
; To use the IDLOC registers, place the following lines in your source
; code in the following format, and change <expression> as desired.
; These lines are currently commented out here and each __IDLOCS line
; should have the preceding semicolon removed when pasted into your
; source code.
;
; <expression> should take the form of B'1111bbbb' or H'Fn'
; where b = user defined bit, or n = user defined nibble.
; Program IDLOC registers
; __IDLOCS _IDLOC0, <expression>
; __IDLOCS _IDLOC1, <expression>
; __IDLOCS _IDLOC2, <expression>
; __IDLOCS _IDLOC3, <expression>
; __IDLOCS _IDLOC4, <expression>
; __IDLOCS _IDLOC5, <expression>
; __IDLOCS _IDLOC6, <expression>
; __IDLOCS _IDLOC7, <expression>
;=======================================================================
;
; Configuration Bits
;
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads and writes,
; and for programming configuration words.
_CONFIG1L EQU H'300000'
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3L EQU H'300004'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG4H EQU H'300007'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
; To use the Configuration Bits, place the following lines in your
; source code in the following format, and change the configuration
; value to the desired setting (such as WDT_OFF to WDT_ON). These are
; currently commented out here and each __CONFIG line should have the
; preceding semicolon removed when pasted into your source code.
; __CONFIG _CONFIG1L, 0x00
; __CONFIG _CONFIG1H, 0x00
; __CONFIG _CONFIG2L, 0x00
; __CONFIG _CONFIG2H, _WDT_ON_2H
; __CONFIG _CONFIG3L, 0x00
; __CONFIG _CONFIG3H, _MCLRE_ON_3H
; __CONFIG _CONFIG4L, _BKBUG_OFF_4L | _STVR_ON_4L
; __CONFIG _CONFIG4H, 0x00
; __CONFIG _CONFIG5L, _CP01_OFF_5L | _CP23_OFF_5L
; __CONFIG _CONFIG5H, _CPB_OFF_5H | _CPD_OFF_5H
; __CONFIG _CONFIG6L, _WRT01_OFF_6L | _WRT23_OFF_6L
; __CONFIG _CONFIG6H, _WRTC_OFF_6H | _WRTB_OFF_6H | _WRTD_OFF_6H
; __CONFIG _CONFIG7L, _EBTR01_OFF_7L | _EBTR23_OFF_7L
; __CONFIG _CONFIG7H, _EBTRB_OFF_7H
;Configuration Byte 2H Options
_WDT_ON_2H EQU H'01' ; Watch Dog Timer enabled
_WDT_OFF_2H EQU H'00' ; Watch Dog Timer disabled
;Configuration Byte 3H Options
_MCLRE_ON_3H EQU H'80' ; MCLR enabled, RA5 input disabled
_MCLRE_OFF_3H EQU H'00' ; MCLR disabled, RA5 input enabled
;Configuration Byte 4L Options
_BKBUG_ON_4L EQU H'00' ; BacKground deBUGger enabled
_BKBUG_OFF_4L EQU H'80' ; BacKground deBUGger disabled
_STVR_ON_4L EQU H'01' ; Stack over/underflow Reset enabled
_STVR_OFF_4L EQU H'00' ; Stack over/underflow Reset disabled
;Configuration Byte 5L Options
; Protect program memory blocks from programmer reads and writes (see Config Byte 6L)
_CP01_ON_5L EQU H'00' ; Blocks 0 & 1 protected
_CP01_OFF_5L EQU H'01' ; Blocks 0 & 1 readable/ may be writable
_CP23_ON_5L EQU H'00' ; Blocks 2 & 3 protected
_CP23_OFF_5L EQU H'02' ; Blocks 2 & 3 readable/ may be writable
;Configuration Byte 5H Options
; Protect blocks from programmer reads and writes (see Config Byte 6H)
_CPB_ON_5H EQU H'00' ; Boot Block protected
_CPB_OFF_5H EQU H'40' ; Boot Block readable / may be writable
_CPD_ON_5H EQU H'00' ; Data EE memory protected
_CPD_OFF_5H EQU H'80' ; Data EE memory readable / may be writable
;Configuration Byte 6L Options
; Protect program memory blocks from table writes and programmer writes
_WRT01_ON_6L EQU H'00' ; Block 0 & 1 write protected
_WRT01_OFF_6L EQU H'01' ; Block 0 & 1 writable
_WRT23_ON_6L EQU H'00' ; Block 2 & 3 write protected
_WRT23_OFF_6L EQU H'02' ; Block 2 & 3 writable
;Configuration Byte 6H Options
; Protect blocks from table writes and programmer writes
_WRTC_ON_6H EQU H'00' ; Config registers write protected
_WRTC_OFF_6H EQU H'20' ; Config registers writable
_WRTB_ON_6H EQU H'00' ; Boot block write protected
_WRTB_OFF_6H EQU H'40' ; Boot block writable
_WRTD_ON_6H EQU H'00' ; Data EE write protected
_WRTD_OFF_6H EQU H'80' ; Data EE writable
;Configuration Byte 7L Options
; Protect program memory blocks from table reads executed from other blocks
_EBTR01_ON_7L EQU H'00' ; Block 0 & 1 protected
_EBTR01_OFF_7L EQU H'01' ; Block 0 & 1 readable
_EBTR23_ON_7L EQU H'00' ; Block 2 & 3 protected
_EBTR23_OFF_7L EQU H'02' ; Block 2 & 3 readable
;Configuration Byte 7H Options
; Protect block from table reads executed in other blocks
_EBTRB_ON_7H EQU H'00' ; Boot block read protected
_EBTRB_OFF_7H EQU H'40' ; Boot block readable
;=======================================================================
;
; Device ID registers
;
; The following is an assignment of address values for the Device ID
; registers for the purpose of table reads.
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
; Device ID registers hold device ID and revision number and are
; read-only
;
;Device ID Register 1
; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0
;
;Device ID Register 2
; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3
;=======================================================================
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