📄 p18f8627.inc
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IOFS EQU H'0002'
OSTS EQU H'0003'
IRCF0 EQU H'0004'
IRCF1 EQU H'0005'
IRCF2 EQU H'0006'
IDLEN EQU H'0007'
FLTS EQU H'0002'
;----- T0CON Bits -----------------------------------------------------
T0PS0 EQU H'0000'
T0PS1 EQU H'0001'
T0PS2 EQU H'0002'
PSA EQU H'0003'
T0SE EQU H'0004'
T0CS EQU H'0005'
T08BIT EQU H'0006'
TMR0ON EQU H'0007'
T0PS3 EQU H'0003'
;----- STATUS Bits -----------------------------------------------------
C EQU H'0000'
DC EQU H'0001'
Z EQU H'0002'
OV EQU H'0003'
N EQU H'0004'
;----- INTCON3 Bits -----------------------------------------------------
INT1F EQU H'0000'
INT2F EQU H'0001'
INT3F EQU H'0002'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT3E EQU H'0005'
INT1P EQU H'0006'
INT2P EQU H'0007'
INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT3IF EQU H'0002'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT3IE EQU H'0005'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
INT3P EQU H'0001'
T0IP EQU H'0002'
INTEDG3 EQU H'0003'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
INT3IP EQU H'0001'
TMR0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0F EQU H'0001'
T0IF EQU H'0002'
RBIE EQU H'0003'
INT0E EQU H'0004'
T0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKFUL EQU H'0007'
SP0 EQU H'0000'
SP1 EQU H'0001'
SP2 EQU H'0002'
SP3 EQU H'0003'
SP4 EQU H'0004'
STKOVF EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0F7A'-H'0F7B'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Oscillator Selection bits:
; OSC = LP LP oscillator
; OSC = XT XT oscillator
; OSC = HS HS oscillator
; OSC = RC External RC oscillator, CLKO function on RA6
; OSC = EC EC oscillator, CLKO function on RA6
; OSC = ECIO6 EC oscillator, port function on RA6
; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
; OSC = RCIO6 External RC oscillator, port function on RA6
; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF Fail-Safe Clock Monitor disabled
; FCMEN = ON Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit:
; IESO = OFF Two-Speed Start-up disabled
; IESO = ON Two-Speed Start-up enabled
;
; Power-up Timer Enable bit:
; PWRT = ON PWRT enabled
; PWRT = OFF PWRT disabled
;
; Brown-out Reset Enable bits:
; BOREN = OFF Brown-out Reset disabled in hardware and software
; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
;
; Brown-out Voltage bits:
; BORV = 0 Maximum setting
; BORV = 1
; BORV = 2
; BORV = 3 Minimum setting
;
; Watchdog Timer Enable bit:
; WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
; WDT = ON WDT enabled
;
; Watchdog Timer Postscale Select bits:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; Processor Data Memory Mode Select bits:
; MODE = EM Extended Microcontroller mode
; MODE = MPB Microprocessor with Boot Block mode
; MODE = MP Microprocessor mode
; MODE = MC Microcontroller mode
;
; Address Bus Width Select bits:
; ADDRBW = ADDR8BIT 8-bit Address Bus
; ADDRBW = ADDR12BIT 12-bit Address Bus
; ADDRBW = ADDR16BIT 16-bit Address Bus
; ADDRBW = ADDR20BIT 20-bit Address Bus
;
; Data Bus Width Select bit:
; DATABW = DATA8BIT 8-bit External Bus mode
; DATABW = DATA16BIT 16-bit External Bus mode
;
; External Bus Data Wait Enable bit:
; WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits
; WAIT = OFF Wait selections are unavailable for table reads and table writes
;
; MCLR Pin Enable bit:
; MCLRE = OFF RG5 input pin enabled; MCLR disabled
; MCLRE = ON MCLR pin enabled; RG5 input pin disabled
;
; Low-Power Timer1 Oscillator Enable bit:
; LPT1OSC = OFF Timer1 configured for higher power operation
; LPT1OSC = ON Timer1 configured for low-power operation
;
; ECCP MUX bit:
; ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively
; ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively
;
; CCP2 MUX bit:
; CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
;
; Stack Full/Underflow Reset Enable bit:
; STVREN = OFF Stack full/underflow will not cause Reset
; STVREN = ON Stack full/underflow will cause Reset
;
; Single-Supply ICSP Enable bit:
; LVP = OFF Single-Supply ICSP disabled
; LVP = ON Single-Supply ICSP enabled
;
; Boot Block Size Select bits:
; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
;
; Extended Instruction Set Enable bit:
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
;
; Background Debugger Enable bit:
; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;
; Code Protection bit Block 0:
; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
;
; Code Protection bit Block 1:
; CP1 = ON Block 1 (004000-007FFFh) code-protected
; CP1 = OFF Block 1 (004000-007FFFh) not code-protected
;
; Code Protection bit Block 2:
; CP2 = ON Block 2 (008000-00BFFFh) code-protected
; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
;
; Code Protection bit Block 3:
; CP3 = ON Block 3 (00C000-00FFFFh) code-protected
; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
;
; Code Protection bit Block 4:
; CP4 = ON Block 4 (010000-013FFFh) code-protected
; CP4 = OFF Block 4 (010000-013FFFh) not code-protected
;
; Code Protection bit Block 5:
; CP5 = ON Block 5 (014000-017FFFh) code-protected
; CP5 = OFF Block 5 (014000-017FFFh) not code-protected
;
; Boot Block Code Protection bit:
; CPB = ON Boot Block (000000-0007FFh) code-protected
; CPB = OFF Boot Block (000000-0007FFh) not code-protected
;
; Data EEPROM Code Protection bit:
; CPD = ON Data EEPROM code-protected
; CPD = OFF Data EEPROM not code-protected
;
; Write Protection bit Block 0:
; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
;
; Write Protection bit Block 1:
; WRT1 = ON Block 1 (004000-007FFFh) write-protected
; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
;
; Write Protection bit Block 2:
; WRT2 = ON Block 2 (008000-00BFFFh) write-protected
; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
;
; Write Protection bit Block 3:
; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
;
; Write Protection bit Block 4:
; WRT4 = ON Block 4 (010000-013FFFh) write-protected
; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected
;
; Write Protection bit Block 5:
; WRT5 = ON Block 5 (014000-017FFFh) write-protected
; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected
;
; Boot Block Write Protection bit:
; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
;
; Configuration Register Write Protection bit:
; WRTC = ON Configuration registers (300000-3000FFh) write-protected
; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
;
; Data EEPROM Write Protection bit:
; WRTD = ON Data EEPROM write-protected
; WRTD = OFF Data EEPROM not write-protected
;
; Table Read Protection bit Block 0:
; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks
; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 1:
; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 2:
; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 3:
; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 4:
; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks
; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 5:
; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks
; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
;
; Boot Block Table Read Protection bit:
; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3L 300004h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
; CONFIG5H 300009h
; CONFIG6L 30000Ah
; CONFIG6H 30000Bh
; CONFIG7L 30000Ch
; CONFIG7H 30000Dh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3L EQU H'300004'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1H Options --------------------------------------------------
_OSC_LP_1H EQU H'F0' ; LP oscillator
_OSC_XT_1H EQU H'F1' ; XT oscillator
_OSC_HS_1H EQU H'F2' ; HS oscillator
_OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6
_OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6
_OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6
_OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
_OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6
_OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7
_OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled
_IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_0_2L EQU H'E7' ; Maximum setting
_BORV_1_2L EQU H'EF' ;
_BORV_2_2L EQU H'F7' ;
_BORV_3_2L EQU H'FF' ; Minimum setting
;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit)
_WDT_ON_2H EQU H'FF' ; WDT enabled
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H E⌨️ 快捷键说明
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