📄 p18f452.inc
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;
; Brown-out Reset:
; BOR = OFF Disabled
; BOR = ON Enabled
;
; Brown-out Voltage:
; BORV = 45 4.5V
; BORV = 42 4.2V
; BORV = 27 2.7V
; BORV = 25 2.5V
;
; Watchdog Timer:
; WDT = OFF Disabled
; WDT = ON Enabled
;
; Watchdog Postscaler:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
;
; CCP2 MUX:
; CCP2MUX = OFF Disable (RB3)
; CCP2MUX = ON Enable (RC1)
;
; Stack Overflow Reset:
; STVR = OFF Disabled
; STVR = ON Enabled
;
; Low Voltage ICSP:
; LVP = OFF Disabled
; LVP = ON Enabled
;
; Background Debugger Enable:
; DEBUG = ON Enabled
; DEBUG = OFF Disabled
;
; Code Protection Block 0:
; CP0 = ON Enabled
; CP0 = OFF Disabled
;
; Code Protection Block 1:
; CP1 = ON Enabled
; CP1 = OFF Disabled
;
; Code Protection Block 2:
; CP2 = ON Enabled
; CP2 = OFF Disabled
;
; Code Protection Block 3:
; CP3 = ON Enabled
; CP3 = OFF Disabled
;
; Boot Block Code Protection:
; CPB = ON Enabled
; CPB = OFF Disabled
;
; Data EEPROM Code Protection:
; CPD = ON Enabled
; CPD = OFF Disabled
;
; Write Protection Block 0:
; WRT0 = ON Enabled
; WRT0 = OFF Disabled
;
; Write Protection Block 1:
; WRT1 = ON Enabled
; WRT1 = OFF Disabled
;
; Write Protection Block 2:
; WRT2 = ON Enabled
; WRT2 = OFF Disabled
;
; Write Protection Block 3:
; WRT3 = ON Enabled
; WRT3 = OFF Disabled
;
; Boot Block Write Protection:
; WRTB = ON Enabled
; WRTB = OFF Disabled
;
; Configuration Register Write Protection:
; WRTC = ON Enabled
; WRTC = OFF Disabled
;
; Data EEPROM Write Protection:
; WRTD = ON Enabled
; WRTD = OFF Disabled
;
; Table Read Protection Block 0:
; EBTR0 = ON Enabled
; EBTR0 = OFF Disabled
;
; Table Read Protection Block 1:
; EBTR1 = ON Enabled
; EBTR1 = OFF Disabled
;
; Table Read Protection Block 2:
; EBTR2 = ON Enabled
; EBTR2 = OFF Disabled
;
; Table Read Protection Block 3:
; EBTR3 = ON Enabled
; EBTR3 = OFF Disabled
;
; Boot Block Table Read Protection:
; EBTRB = ON Enabled
; EBTRB = OFF Disabled
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; Data Sheet Include File Address
; CONFIG1L = Configuration Byte 1L 300000h
; CONFIG1H = Configuration Byte 1H 300001h
; CONFIG2L = Configuration Byte 2L 300002h
; CONFIG2H = Configuration Byte 2H 300003h
; CONFIG3L = Configuration Byte 3L 300004h
; CONFIG3H = Configuration Byte 3H 300005h
; CONFIG4L = Configuration Byte 4L 300006h
; CONFIG4H = Configuration Byte 4H 300007h
; CONFIG5L = Configuration Byte 5L 300008h
; CONFIG5H = Configuration Byte 5H 300009h
; CONFIG6L = Configuration Byte 6L 30000ah
; CONFIG6H = Configuration Byte 6H 30000bh
; CONFIG7L = Configuration Byte 7L 30000ch
; CONFIG7H = Configuration Byte 7H 30000dh
;
;==========================================================================
;Configuration Byte 1H Options
_OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable
_OSCS_OFF_1H EQU H'FF'
_LP_OSC_1H EQU H'F8' ; Oscillator type
_XT_OSC_1H EQU H'F9'
_HS_OSC_1H EQU H'FA'
_RC_OSC_1H EQU H'FB'
_EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4
_ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6)
_HSPLL_OSC_1H EQU H'FE' ; HS PLL
_RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6)
;Configuration Byte 2L Options
_BOR_ON_2L EQU H'FF' ; Brown-out Reset enable
_BOR_OFF_2L EQU H'FD'
_PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable
_PWRT_ON_2L EQU H'FE'
_BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v
_BORV_27_2L EQU H'FB' ; 2.7v
_BORV_42_2L EQU H'F7' ; 4.2v
_BORV_45_2L EQU H'F3' ; 4.5v
;Configuration Byte 2H Options
_WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable
_WDT_OFF_2H EQU H'FE'
_WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count
_WDTPS_64_2H EQU H'FD'
_WDTPS_32_2H EQU H'FB'
_WDTPS_16_2H EQU H'F9'
_WDTPS_8_2H EQU H'F7'
_WDTPS_4_2H EQU H'F5'
_WDTPS_2_2H EQU H'F3'
_WDTPS_1_2H EQU H'F1'
;Configuration Byte 3H Options
_CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable
_CCP2MX_OFF_3H EQU H'FE'
;Configuration Byte 4L Options
_STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable
_STVR_OFF_4L EQU H'FE'
_LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable
_LVP_OFF_4L EQU H'FB'
_DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable
_DEBUG_OFF_4L EQU H'FF'
;Configuration Byte 5L Options
_CP0_ON_5L EQU H'FE' ; Code protect user block enable
_CP0_OFF_5L EQU H'FF'
_CP1_ON_5L EQU H'FD'
_CP1_OFF_5L EQU H'FF'
_CP2_ON_5L EQU H'FB'
_CP2_OFF_5L EQU H'FF'
_CP3_ON_5L EQU H'F7'
_CP3_OFF_5L EQU H'FF'
;Configuration Byte 5H Options
_CPB_ON_5H EQU H'BF' ; Code protect boot block enable
_CPB_OFF_5H EQU H'FF'
_CPD_ON_5H EQU H'7F' ; Code protect Data EE enable
_CPD_OFF_5H EQU H'FF'
;Configuration Byte 6L Options
_WRT0_ON_6L EQU H'FE' ; Write protect user block enable
_WRT0_OFF_6L EQU H'FF'
_WRT1_ON_6L EQU H'FD'
_WRT1_OFF_6L EQU H'FF'
_WRT2_ON_6L EQU H'FB'
_WRT2_OFF_6L EQU H'FF'
_WRT3_ON_6L EQU H'F7'
_WRT3_OFF_6L EQU H'FF'
;Configuration Byte 6H Options
_WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable
_WRTC_OFF_6H EQU H'FF'
_WRTB_ON_6H EQU H'BF' ; Write protect boot block enable
_WRTB_OFF_6H EQU H'FF'
_WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable
_WRTD_OFF_6H EQU H'FF'
;Configuration Byte 7L Options
_EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable
_EBTR0_OFF_7L EQU H'FF'
_EBTR1_ON_7L EQU H'FD'
_EBTR1_OFF_7L EQU H'FF'
_EBTR2_ON_7L EQU H'FB'
_EBTR2_OFF_7L EQU H'FF'
_EBTR3_ON_7L EQU H'F7'
_EBTR3_OFF_7L EQU H'FF'
;Configuration Byte 7H Options
_EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable
_EBTRB_OFF_7H EQU H'FF'
; To use the Configuration Bits, place the following lines in your source code
; in the following format, and change the configuration value to the desired
; setting (such as CP_OFF to CP_ON). These are currently commented out here
; and each __CONFIG line should have the preceding semicolon removed when
; pasted into your source code.
; The following is a assignment of address values for all of the configuration
; registers for the purpose of table reads
_CONFIG1L EQU H'300000'
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3L EQU H'300004'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG4H EQU H'300007'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
;Program Configuration Register 1H
; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H
;Program Configuration Register 2L
; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L
;Program Configuration Register 2H
; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H
;Program Configuration Register 3H
; __CONFIG _CONFIG3H, _CCP2MX_ON_3H
;Program Configuration Register 4L
; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L
;Program Configuration Register 5L
; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L
;Program Configuration Register 5H
; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H
;Program Configuration Register 6L
; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L
;Program Configuration Register 6H
; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H
;Program Configuration Register 7L
; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L
;Program Configuration Register 7H
; __CONFIG _CONFIG7H, _EBTRB_OFF_7H
;ID Locations Register 0
; __IDLOCS _IDLOC0, <expression>
;ID Locations Register 1
; __IDLOCS _IDLOC1, <expression>
;ID Locations Register 2
; __IDLOCS _IDLOC2, <expression>
;ID Locations Register 3
; __IDLOCS _IDLOC3, <expression>
;ID Locations Register 4
; __IDLOCS _IDLOC4, <expression>
;ID Locations Register 5
; __IDLOCS _IDLOC5, <expression>
;ID Locations Register 6
; __IDLOCS _IDLOC6, <expression>
;ID Locations Register 7
; __IDLOCS _IDLOC7, <expression>
;Device ID registers hold device ID and revision number and can only be read
;Device ID Register 1
; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0
;Device ID Register 2
; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3
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