📄 p18f85j50.inc
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ACQT0 EQU H'0003'
ACQT1 EQU H'0004'
ACQT2 EQU H'0005'
ADCAL EQU H'0006'
ADFM EQU H'0007'
;----- ANCON0 Bits -----------------------------------------------------
PCFG0 EQU H'0000'
PCFG1 EQU H'0001'
PCFG2 EQU H'0002'
PCFG3 EQU H'0003'
PCFG4 EQU H'0004'
PCFG5 EQU H'0005'
PCFG6 EQU H'0006'
PCFG7 EQU H'0007'
;----- ADCON0 Bits -----------------------------------------------------
DONE EQU H'0001'
GO_DONE EQU H'0001'
ADON EQU H'0000'
GO EQU H'0001'
CHS0 EQU H'0002'
CHS1 EQU H'0003'
CHS2 EQU H'0004'
CHS3 EQU H'0005'
VCFG0 EQU H'0006'
VCFG1 EQU H'0007'
NOT_DONE EQU H'0001'
;----- ANCON1 Bits -----------------------------------------------------
PCFG8 EQU H'0000'
PCFG9 EQU H'0001'
PCFG10 EQU H'0002'
PCFG11 EQU H'0003'
PCFG12 EQU H'0004'
PCFG13 EQU H'0005'
PCFG14 EQU H'0006'
PCFG15 EQU H'0007'
;----- SSP1CON2 Bits -----------------------------------------------------
SEN EQU H'0000'
RSEN EQU H'0001'
PEN EQU H'0002'
RCEN EQU H'0003'
ACKEN EQU H'0004'
ACKDT EQU H'0005'
ACKSTAT EQU H'0006'
GCEN EQU H'0007'
ADMSK1 EQU H'0001'
ADMSK2 EQU H'0002'
ADMSK3 EQU H'0003'
ADMSK4 EQU H'0004'
ADMSK5 EQU H'0005'
;----- SSPCON2 Bits -----------------------------------------------------
SEN EQU H'0000'
RSEN EQU H'0001'
PEN EQU H'0002'
RCEN EQU H'0003'
ACKEN EQU H'0004'
ACKDT EQU H'0005'
ACKSTAT EQU H'0006'
GCEN EQU H'0007'
ADMSK1 EQU H'0001'
ADMSK2 EQU H'0002'
ADMSK3 EQU H'0003'
ADMSK4 EQU H'0004'
ADMSK5 EQU H'0005'
;----- SSP1CON1 Bits -----------------------------------------------------
SSPM0 EQU H'0000'
SSPM1 EQU H'0001'
SSPM2 EQU H'0002'
SSPM3 EQU H'0003'
CKP EQU H'0004'
SSPEN EQU H'0005'
SSPOV EQU H'0006'
WCOL EQU H'0007'
;----- SSPCON1 Bits -----------------------------------------------------
SSPM0 EQU H'0000'
SSPM1 EQU H'0001'
SSPM2 EQU H'0002'
SSPM3 EQU H'0003'
CKP EQU H'0004'
SSPEN EQU H'0005'
SSPOV EQU H'0006'
WCOL EQU H'0007'
;----- SSP1STAT Bits -----------------------------------------------------
BF EQU H'0000'
UA EQU H'0001'
R_W EQU H'0002'
S EQU H'0003'
P EQU H'0004'
D_A EQU H'0005'
CKE EQU H'0006'
SMP EQU H'0007'
I2C_READ EQU H'0002'
I2C_START EQU H'0003'
I2C_STOP EQU H'0004'
I2C_DAT EQU H'0005'
NOT_W EQU H'0002'
NOT_A EQU H'0005'
NOT_WRITE EQU H'0002'
NOT_ADDRESS EQU H'0005'
READ_WRITE EQU H'0002'
DATA_ADDRESS EQU H'0005'
R EQU H'0002'
D EQU H'0005'
;----- SSPSTAT Bits -----------------------------------------------------
BF EQU H'0000'
UA EQU H'0001'
R_W EQU H'0002'
S EQU H'0003'
P EQU H'0004'
D_A EQU H'0005'
CKE EQU H'0006'
SMP EQU H'0007'
I2C_READ EQU H'0002'
I2C_START EQU H'0003'
I2C_STOP EQU H'0004'
I2C_DAT EQU H'0005'
NOT_W EQU H'0002'
NOT_A EQU H'0005'
NOT_WRITE EQU H'0002'
NOT_ADDRESS EQU H'0005'
READ_WRITE EQU H'0002'
DATA_ADDRESS EQU H'0005'
R EQU H'0002'
D EQU H'0005'
;----- T2CON Bits -----------------------------------------------------
T2CKPS0 EQU H'0000'
T2CKPS1 EQU H'0001'
TMR2ON EQU H'0002'
T2OUTPS0 EQU H'0003'
T2OUTPS1 EQU H'0004'
T2OUTPS2 EQU H'0005'
T2OUTPS3 EQU H'0006'
;----- MEMCON Bits -----------------------------------------------------
WM0 EQU H'0000'
WM1 EQU H'0001'
WAIT0 EQU H'0004'
WAIT1 EQU H'0005'
EDBIS EQU H'0007'
;----- PADCFG1 Bits -----------------------------------------------------
PMPTTL EQU H'0000'
;----- ODCON3 Bits -----------------------------------------------------
SPI1OD EQU H'0000'
SPI2OD EQU H'0001'
;----- T1CON Bits -----------------------------------------------------
TMR1ON EQU H'0000'
TMR1CS EQU H'0001'
T1SYNC EQU H'0002'
T1OSCEN EQU H'0003'
T1CKPS0 EQU H'0004'
T1CKPS1 EQU H'0005'
T1RUN EQU H'0006'
RD16 EQU H'0007'
T1INSYNC EQU H'0002'
NOT_T1SYNC EQU H'0002'
;----- ODCON2 Bits -----------------------------------------------------
USART1OD EQU H'0000'
USART2OD EQU H'0001'
U1OD EQU H'0000'
U2OD EQU H'0001'
;----- ODCON1 Bits -----------------------------------------------------
ECCP1OD EQU H'0000'
ECCP2OD EQU H'0001'
ECCP3OD EQU H'0002'
CCP4OD EQU H'0003'
CCP5OD EQU H'0004'
;----- RCON Bits -----------------------------------------------------
NOT_BOR EQU H'0000'
NOT_POR EQU H'0001'
NOT_PD EQU H'0002'
NOT_TO EQU H'0003'
NOT_RI EQU H'0004'
NOT_CM EQU H'0005'
IPEN EQU H'0007'
BOR EQU H'0000'
POR EQU H'0001'
PD EQU H'0002'
TO EQU H'0003'
RI EQU H'0004'
CM EQU H'0005'
;----- CM2CON Bits -----------------------------------------------------
C1CH0 EQU H'0000'
C1CH1 EQU H'0001'
CREF EQU H'0002'
EVPOL0 EQU H'0003'
EVPOL1 EQU H'0004'
CPOL EQU H'0005'
COE EQU H'0006'
CON EQU H'0007'
CCH0 EQU H'0000'
CCH1 EQU H'0001'
;----- CM2CON1 Bits -----------------------------------------------------
C1CH0 EQU H'0000'
C1CH1 EQU H'0001'
CREF EQU H'0002'
EVPOL0 EQU H'0003'
EVPOL1 EQU H'0004'
CPOL EQU H'0005'
COE EQU H'0006'
CON EQU H'0007'
CCH0 EQU H'0000'
CCH1 EQU H'0001'
;----- CM1CON Bits -----------------------------------------------------
C1CH0 EQU H'0000'
C1CH1 EQU H'0001'
CREF EQU H'0002'
EVPOL0 EQU H'0003'
EVPOL1 EQU H'0004'
CPOL EQU H'0005'
COE EQU H'0006'
CON EQU H'0007'
CCH0 EQU H'0000'
CCH1 EQU H'0001'
;----- CM1CON1 Bits -----------------------------------------------------
C1CH0 EQU H'0000'
C1CH1 EQU H'0001'
CREF EQU H'0002'
EVPOL0 EQU H'0003'
EVPOL1 EQU H'0004'
CPOL EQU H'0005'
COE EQU H'0006'
CON EQU H'0007'
CCH0 EQU H'0000'
CCH1 EQU H'0001'
;----- OSCCON Bits -----------------------------------------------------
SCS0 EQU H'0000'
SCS1 EQU H'0001'
IOFS EQU H'0002'
OSTS EQU H'0003'
IRCF0 EQU H'0004'
IRCF1 EQU H'0005'
IRCF2 EQU H'0006'
IDLEN EQU H'0007'
FLTS EQU H'0002'
;----- REFOCON Bits -----------------------------------------------------
RODIV0 EQU H'0000'
RODIV1 EQU H'0001'
RODIV2 EQU H'0002'
RODIV3 EQU H'0003'
ROSEL EQU H'0004'
ROSSLP EQU H'0005'
ROON EQU H'0007'
;----- T0CON Bits -----------------------------------------------------
T0PS0 EQU H'0000'
T0PS1 EQU H'0001'
T0PS2 EQU H'0002'
PSA EQU H'0003'
T0SE EQU H'0004'
T0CS EQU H'0005'
T08BIT EQU H'0006'
TMR0ON EQU H'0007'
T0PS3 EQU H'0003'
;----- STATUS Bits -----------------------------------------------------
C EQU H'0000'
DC EQU H'0001'
Z EQU H'0002'
OV EQU H'0003'
N EQU H'0004'
;----- INTCON3 Bits -----------------------------------------------------
INT1F EQU H'0000'
INT2F EQU H'0001'
INT3F EQU H'0002'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT3E EQU H'0005'
INT1P EQU H'0006'
INT2P EQU H'0007'
INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT3IF EQU H'0002'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT3IE EQU H'0005'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
INT3P EQU H'0001'
T0IP EQU H'0002'
INTEDG3 EQU H'0003'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
INT3IP EQU H'0001'
TMR0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0F EQU H'0001'
T0IF EQU H'0002'
RBIE EQU H'0003'
INT0E EQU H'0004'
T0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKOVF EQU H'0007'
SP0 EQU H'0000'
SP1 EQU H'0001'
SP2 EQU H'0002'
SP3 EQU H'0003'
SP4 EQU H'0004'
STKFUL EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Background Debugger Enable bit:
; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
;
; Extended Instruction Set Enable bit:
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
;
; Stack Overflow/Underflow Reset Enable bit:
; STVREN = OFF Reset on stack overflow/underflow disabled
; STVREN = ON Reset on stack overflow/underflow enabled
;
; PLL Prescaler Selection bits:
; PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
; PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
; PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
; PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
; PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
; PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
; PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
;
; Watchdog Timer Enable bit:
; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
; WDTEN = ON WDT enabled
;
; Code Protection bit:
; CP0 = ON Program memory is code-protected
; CP0 = OFF Pro⌨️ 快捷键说明
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