📄 p18c601.inc
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;----- ADCON0 Bits --------------------------------------------------------
CHS3 EQU H'0005'
CHS2 EQU H'0004'
CHS1 EQU H'0003'
CHS0 EQU H'0002'
GO EQU H'0001'
NOT_DONE EQU H'0001'
DONE EQU H'0001'
GO_DONE EQU H'0001'
ADON EQU H'0000'
;----- ADCON1 Bits --------------------------------------------------------
VCFG1 EQU H'0005'
VCFG0 EQU H'0004'
PCFG3 EQU H'0003'
PCFG2 EQU H'0002'
PCFG1 EQU H'0001'
PCFG0 EQU H'0000'
;----- ADCON2 Bits --------------------------------------------------------
ADFM EQU H'0007'
ADCS2 EQU H'0002'
ADCS1 EQU H'0001'
ADCS0 EQU H'0000'
;----- CCP1CON Bits -------------------------------------------------------
DC1B1 EQU H'0005'
CCP1X EQU H'0005' ; For backward compatibility
DC1B0 EQU H'0004'
CCP1Y EQU H'0004' ; For backward compatibility
CCP1M3 EQU H'0003'
CCP1M2 EQU H'0002'
CCP1M1 EQU H'0001'
CCP1M0 EQU H'0000'
;----- CCP2CON Bits -------------------------------------------------------
DC2B1 EQU H'0005'
CCP2X EQU H'0005' ; For backward compatibility
DCCPX EQU H'0005'
DC2B0 EQU H'0004'
CCP2Y EQU H'0004' ; For backward compatibility
CCP2M3 EQU H'0003'
CCP2M2 EQU H'0002'
CCP2M1 EQU H'0001'
CCP2M0 EQU H'0000'
;----- T3CON Bits ---------------------------------------------------------
RD16 EQU H'0007'
T3CCP2 EQU H'0006'
T3CKPS1 EQU H'0005'
T3CKPS0 EQU H'0004'
T3CCP1 EQU H'0003'
T3SYNC EQU H'0002'
NOT_T3SYNC EQU H'0002'
T3INSYNC EQU H'0002' ; Backward compatibility only
TMR3CS EQU H'0001'
TMR3ON EQU H'0000'
;----- PSPCON Bits ---------------------------------------------------------
CMLK1 EQU H'0001'
CMLK0 EQU H'0000'
;----- TXSTA Bits -------------------------------------------------------
CSRC EQU H'0007'
TX9 EQU H'0006'
TXEN EQU H'0005'
SYNC EQU H'0004'
BRGH EQU H'0002'
TRMT EQU H'0001'
TX9D EQU H'0000'
;----- RCSTA Bits -------------------------------------------------------
SPEN EQU H'0007'
RX9 EQU H'0006'
SREN EQU H'0005'
CREN EQU H'0004'
ADEN EQU H'0003'
FERR EQU H'0002'
OERR EQU H'0001'
RX9D EQU H'0000'
;----- IPR2 Bits ----------------------------------------------------------
BCLIP EQU H'0003'
LVDIP EQU H'0002'
TMR3IP EQU H'0001'
CCP2IP EQU H'0000'
;----- PIR2 Bits ----------------------------------------------------------
BCLIF EQU H'0003'
LVDIF EQU H'0002'
TMR3IF EQU H'0001'
CCP2IF EQU H'0000'
;----- PIE2 Bits ----------------------------------------------------------
BCLIE EQU H'0003'
LVDIE EQU H'0002'
TMR3IE EQU H'0001'
CCP2IE EQU H'0000'
;----- IPR1 Bits ----------------------------------------------------------
ADIP EQU H'0006'
RCIP EQU H'0005'
TXIP EQU H'0004'
SSPIP EQU H'0003'
CCP1IP EQU H'0002'
TMR2IP EQU H'0001'
TMR1IP EQU H'0000'
;----- PIR1 Bits ----------------------------------------------------------
ADIF EQU H'0006'
RCIF EQU H'0005'
TXIF EQU H'0004'
SSPIF EQU H'0003'
CCP1IF EQU H'0002'
TMR2IF EQU H'0001'
TMR1IF EQU H'0000'
;----- PIE1 Bits ----------------------------------------------------------
ADIE EQU H'0006'
RCIE EQU H'0005'
TXIE EQU H'0004'
SSPIE EQU H'0003'
CCP1IE EQU H'0002'
TMR2IE EQU H'0001'
TMR1IE EQU H'0000'
;----- MEMCON Bits ----------------------------------------------------------
EBDIS EQU H'0007'
PGRM EQU H'0006'
WAIT1 EQU H'0005'
WAIT0 EQU H'0004'
WM1 EQU H'0001'
WM0 EQU H'0000'
;==========================================================================
;
; I/O Pin Name Definitions
;
;==========================================================================
;----- PORTA ------------------------------------------------------------------
RA0 EQU 0
AN0 EQU 0
RA1 EQU 1
AN1 EQU 1
RA2 EQU 2
AN2 EQU 2
VREFN EQU 2
RA3 EQU 3
AN3 EQU 3
VREFP EQU 3
RA4 EQU 4
T0CKI EQU 4
RA5 EQU 5
AN4 EQU 5
SS EQU 5
LVDIN EQU 5
;----- PORTB ------------------------------------------------------------------
RB0 EQU 0
INT0 EQU 0
RB1 EQU 1
INT1 EQU 1
RB2 EQU 2
INT2 EQU 2
RB3 EQU 3
CCP2 EQU 3
RB4 EQU 4
RB5 EQU 5
RB6 EQU 6
RB7 EQU 7
;----- PORTC ------------------------------------------------------------------
RC0 EQU 0
T1OSO EQU 0
T1CKI EQU 0
RC1 EQU 1
T1OSI EQU 1
RC2 EQU 2
CCP1 EQU 2
RC3 EQU 3
SCK EQU 3
SCL EQU 3
RC4 EQU 4
SDI EQU 4
SDA EQU 4
RC5 EQU 5
SDO EQU 5
RC6 EQU 6
TX EQU 6
CK EQU 6
RC7 EQU 7
RX EQU 7
;****DT EQU 7 ;*** Not Available due to conflict with
;*** Define Table (DT) directive
;----- PORTD ------------------------------------------------------------------
RD0 EQU 0
AD0 EQU 0
RD1 EQU 1
AD1 EQU 1
RD2 EQU 2
AD2 EQU 2
RD3 EQU 3
AD3 EQU 3
RD4 EQU 4
AD4 EQU 4
RD5 EQU 5
AD5 EQU 5
RD6 EQU 6
AD6 EQU 6
RD7 EQU 7
AD7 EQU 7
;----- PORTE ------------------------------------------------------------------
RE0 EQU 0
AD8 EQU 0
RE1 EQU 1
AD9 EQU 1
RE2 EQU 2
AD10 EQU 2
RE3 EQU 3
AD11 EQU 3
RE4 EQU 4
AD12 EQU 4
RE5 EQU 5
AD13 EQU 5
RE6 EQU 6
AD14 EQU 6
RE7 EQU 7
AD15 EQU 7
;----- PORTF ------------------------------------------------------------------
RF0 EQU 0
AN5 EQU 0
RF1 EQU 1
AN6 EQU 1
RF2 EQU 2
AN7 EQU 2
RF3 EQU 3
CSIO EQU 3
RF4 EQU 4
AD16 EQU 4
RF5 EQU 5
CS1 EQU 5
RF6 EQU 6
LB EQU 6
RF7 EQU 7
UB EQU 7
;----- PORTG ------------------------------------------------------------------
RG0 EQU 0
ALE EQU 0
RG1 EQU 1
OE EQU 1
RG2 EQU 2
WRL EQU 2
RG3 EQU 3
WRH EQU 3
RG4 EQU 4
BA0 EQU 4
;==========================================================================
;
; RAM Definition
;
;==========================================================================
__MAXRAM H'FFF'
__BADRAM H'400'-H'F7F', H'F9B', H'FA3'-H'FA5'
__BADRAM H'FA8'-H'FAA', H'FB4'-H'FB9', H'FD4'
;==========================================================================
;
; ROM Definition
;
;==========================================================================
__MAXROM H'1FFFFF'
__BADROM H'40000' - H'1FFDFF'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Oscillator Selection:
; OSC = LP LP Oscillator
; OSC = EC EC Oscillator
; OSC = HS HS Oscillator
; OSC = RC RC Oscillator
;
; Power-up Timer:
; PWRT = ON Enable
; PWRT = OFF Disable
;
; External Bus Data Width:
; BW = 8 8-bit External Bus mode
; BW = 16 16-bit External Bus mode
;
; Watchdog Timer:
; WDT = OFF Disabled
; WDT = ON Enabled
;
; Watchdog Timer Postscale Selection:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
;
; Stack Full/Underflow Reset:
; STVR = OFF Disabled
; STVR = ON Enabled
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; Data Sheet Include File Address
; CONFIG1H = Configuration Byte 1H 300001h
; CONFIG2L = Configuration Byte 2L 300002h
; CONFIG2H = Configuration Byte 2H 300003h
; CONFIG4L = Configuration Byte 4L 300006h
;
;==========================================================================
;Configuration Byte 1H Options
_RC_OSC_1H EQU H'FF'
_HS_OSC_1H EQU H'FE' ; Default mode. 4x PLL enabled in S/W
_EC_OSC_1H EQU H'FD' ; External Clock w/OSC2 output divide by 4
_LP_OSC_1H EQU H'FC' ; Oscillator type
;Configuration Byte 2L Options
_BW_16_BIT_2L EQU H'FF' ; Default bus width
_BW_8_BIT_2L EQU H'BF' ;
_PWRT_OFF_2L EQU H'FF' ; Disable Power-up Timer
_PWRT_ON_2L EQU H'FE' ; Enable Power-up Timer
;Configuration Byte 2H Options
_WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable
_WDT_OFF_2H EQU H'FE'
_WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count
_WDTPS_64_2H EQU H'FD'
_WDTPS_32_2H EQU H'FB'
_WDTPS_16_2H EQU H'F9'
_WDTPS_8_2H EQU H'F7'
_WDTPS_4_2H EQU H'F5'
_WDTPS_2_2H EQU H'F3'
_WDTPS_1_2H EQU H'F1'
;Configuration Byte 4L Options
_STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable
_STVR_OFF_4L EQU H'FE'
; To use the Configuration Bits, place the following lines in your source code
; in the following format, and change the configuration value to the desired
; setting (such as _HS_OSC_1H). These are currently commented out here
; and each __CONFIG line should have the preceding semicolon removed when
; pasted into your source code.
;Program _CONFIG1H
; __CONFIG _CONFIG1H, _RC_OSC_1H
;Program _CONFIG2L
; __CONFIG _CONFIG2L, _BW_16_BIT_2L & _PWRT_OFF_2L
;Program _CONFIG2H
; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H
;Program _CONFIG4L
; __CONFIG _CONFIG4L, _STVR_ON_4L
; The following is a assignment of address values for all of the configuration
; registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG4L EQU H'300006'
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
;Device ID registers hold device ID and revision number and can only be read
;Device ID Register 1
; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0
;Device ID Register 2
; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3
;==========================================================================
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