📄 p18f6390.inc
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I2C_STOP EQU H'0004'
I2C_DAT EQU H'0005'
NOT_W EQU H'0002'
NOT_A EQU H'0005'
NOT_WRITE EQU H'0002'
NOT_ADDRESS EQU H'0005'
READ_WRITE EQU H'0002'
DATA_ADDRESS EQU H'0005'
R EQU H'0002'
D EQU H'0005'
;----- T2CON Bits -----------------------------------------------------
T2CKPS0 EQU H'0000'
T2CKPS1 EQU H'0001'
TMR2ON EQU H'0002'
T2OUTPS0 EQU H'0003'
T2OUTPS1 EQU H'0004'
T2OUTPS2 EQU H'0005'
T2OUTPS3 EQU H'0006'
;----- T1CON Bits -----------------------------------------------------
TMR1ON EQU H'0000'
TMR1CS EQU H'0001'
NOT_T1SYNC EQU H'0002'
T1OSCEN EQU H'0003'
T1CKPS0 EQU H'0004'
T1CKPS1 EQU H'0005'
T1RUN EQU H'0006'
RD16 EQU H'0007'
T1SYNC EQU H'0002'
T1INSYNC EQU H'0002'
;----- RCON Bits -----------------------------------------------------
NOT_BOR EQU H'0000'
NOT_POR EQU H'0001'
NOT_PD EQU H'0002'
NOT_TO EQU H'0003'
NOT_RI EQU H'0004'
SBOREN EQU H'0006'
IPEN EQU H'0007'
BOR EQU H'0000'
POR EQU H'0001'
PD EQU H'0002'
TO EQU H'0003'
RI EQU H'0004'
;----- WDTCON Bits -----------------------------------------------------
SWDTEN EQU H'0000'
SWDTE EQU H'0000'
;----- HLVDCON Bits -----------------------------------------------------
LVDL0 EQU H'0000'
LVDL1 EQU H'0001'
LVDL2 EQU H'0002'
LVDL3 EQU H'0003'
LVDEN EQU H'0004'
IRVST EQU H'0005'
VDIRMAG EQU H'0007'
LVV0 EQU H'0000'
LVV1 EQU H'0001'
LVV2 EQU H'0002'
LVV3 EQU H'0003'
BGST EQU H'0005'
HLVDL0 EQU H'0000'
HLVDL1 EQU H'0001'
HLVDL2 EQU H'0002'
HLVDL3 EQU H'0003'
HLVDEN EQU H'0004'
;----- OSCCON Bits -----------------------------------------------------
SCS0 EQU H'0000'
SCS1 EQU H'0001'
IOFS EQU H'0002'
OSTS EQU H'0003'
IRCF0 EQU H'0004'
IRCF1 EQU H'0005'
IRCF2 EQU H'0006'
IDLEN EQU H'0007'
FLTS EQU H'0002'
;----- T0CON Bits -----------------------------------------------------
T0PS0 EQU H'0000'
T0PS1 EQU H'0001'
T0PS2 EQU H'0002'
PSA EQU H'0003'
T0SE EQU H'0004'
T0CS EQU H'0005'
T08BIT EQU H'0006'
TMR0ON EQU H'0007'
;----- STATUS Bits -----------------------------------------------------
C EQU H'0000'
DC EQU H'0001'
Z EQU H'0002'
OV EQU H'0003'
N EQU H'0004'
;----- INTCON3 Bits -----------------------------------------------------
INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT3IF EQU H'0002'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT3IE EQU H'0005'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
INT1F EQU H'0000'
INT2F EQU H'0001'
INT3F EQU H'0002'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT3E EQU H'0005'
INT1P EQU H'0006'
INT2P EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
INT3IP EQU H'0001'
TMR0IP EQU H'0002'
INTEDG3 EQU H'0003'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
INT3P EQU H'0001'
T0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
RBIE EQU H'0003'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0F EQU H'0001'
T0IF EQU H'0002'
INT0E EQU H'0004'
T0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKOVF EQU H'0007'
STKFUL EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0300'-H'0F3F'
__BADRAM H'0F5E'-H'0F5F'
__BADRAM H'0F7D'
__BADRAM H'0F87'-H'0F88'
__BADRAM H'0F90'-H'0F91'
__BADRAM H'0F99'-H'0F9A'
__BADRAM H'0F9C'
__BADRAM H'0FA6'-H'0FAA'
__BADRAM H'0FB0'
__BADRAM H'0FB6'-H'0FB9'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Oscillator Selection bits:
; OSC = LP LP oscillator
; OSC = XT XT oscillator
; OSC = HS HS oscillator
; OSC = RC External RC oscillator, CLKO function on RA6
; OSC = EC EC oscillator, CLKO function on RA6
; OSC = ECIO EC oscillator, port function on RA6
; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
; OSC = RCIO External RC oscillator, port function on RA6
; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF Fail-Safe Clock Monitor disabled
; FCMEN = ON Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit:
; IESO = OFF Oscillator Switchover mode disabled
; IESO = ON Oscillator Switchover mode enabled
;
; Power-up Timer Enable bit:
; PWRT = ON PWRT enabled
; PWRT = OFF PWRT disabled
;
; Brown-out Reset Enable bits:
; BOREN = OFF Brown-out Reset disabled in hardware and software
; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
;
; Brown Out Voltage:
; BORV = 0 Maximum Setting
; BORV = 1
; BORV = 2
; BORV = 3 Minimum Setting
;
; Watchdog Timer Enable bit:
; WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
; WDT = ON WDT enabled
;
; Watchdog Timer Postscale Select bits:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; MCLR Pin Enable bit:
; MCLRE = OFF RG5 input pin enabled; MCLR disabled
; MCLRE = ON MCLR pin enabled; RG5 input pin disabled
;
; Low-Power Timer 1 Oscillator Enable bit:
; LPT1OSC = OFF Timer1 configured for higher power operation
; LPT1OSC = ON Timer1 configured for low-power operation
;
; CCP2 MUX bit:
; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7
; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1
;
; Stack Full/Underflow Reset Enable bit:
; STVREN = OFF Stack full/underflow will not cause Reset
; STVREN = ON Stack full/underflow will cause Reset
;
; Extended Instruction Set Enable bit:
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
;
; Background Debugger Enable bit:
; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;
; Code Protection bit:
; CP = ON Program memory block (000000-003FFFh) code-protected
; CP = OFF Program memory block (000000-003FFFh) not code-protected
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
;----- CONFIG1H Options --------------------------------------------------
_OSC_LP_1H EQU H'F0' ; LP oscillator
_OSC_XT_1H EQU H'F1' ; XT oscillator
_OSC_HS_1H EQU H'F2' ; HS oscillator
_OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6
_OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6
_OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6
_OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
_OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6
_OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7
_OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_0_2L EQU H'E7' ; Maximum Setting
_BORV_1_2L EQU H'EF' ;
_BORV_2_2L EQU H'F7' ;
_BORV_3_2L EQU H'FF' ; Minimum Setting
;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit)
_WDT_ON_2H EQU H'FF' ; WDT enabled
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3H Options --------------------------------------------------
_MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled
_LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation
_LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation
_CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7
_CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
_DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
_DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;----- CONFIG5L Options --------------------------------------------------
_CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected
_CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
LIST
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