📄 p18f1331.inc
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STKFUL EQU H'0006'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0100'-H'0F7F'
__BADRAM H'0F94'
__BADRAM H'0F9C'
__BADRAM H'0FAA'
__BADRAM H'0FB1'-H'0FB3'
__BADRAM H'0FB6'-H'0FB7'
__BADRAM H'0FB9'-H'0FBF'
__BADRAM H'0FC5'-H'0FCC'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Oscillator Selection bits:
; OSC = LP LP Oscillator
; OSC = XT XT Oscillator
; OSC = HS HS Oscillator
; OSC = RC External RC oscillator, CLKO function on RA6
; OSC = EC EC oscillator, CLKO function on RA6
; OSC = ECIO EC oscillator, port function on RA6
; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
; OSC = RCIO External RC oscillator, port function on RA6
; OSC = INTIO2 Internal oscillator, port function on RA6 and RA7
; OSC = INTIO1 Internal oscillator, CLKO function on RA6, port function on RA7
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF Fail-Safe Clock Monitor disabled
; FCMEN = ON Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit:
; IESO = OFF Oscillator Switchover mode disabled
; IESO = ON Oscillator Switchover mode enabled
;
; Power-up Timer Enable bit:
; PWRT = ON PWRT enabled
; PWRT = OFF PWRT disabled
;
; Brown-out Reset Enable bits:
; BOR = OFF Brown-out Reset disabled in hardware and software
; BOR = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled)
; BOR = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
; BOR = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled)
;
; Brown-out Voltage bits:
; BORV = 0 Maximum setting
; BORV = 1
; BORV = 2
; BORV = 3 Minimum setting
;
; Watchdog Timer Enable bit:
; WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
; WDT = ON WDT enabled
;
; Watchdog Timer Postscale Select bits:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit):
; HPOL = LOW PWM1, PWM3 and PWM5 are active-low
; HPOL = HIGH PWM1, PWM3 and PWM5 are active-high (default)
;
; Low-Side Transistors Polarity bit (Even PWM Output Polarity Control bit):
; LPOL = LOW PWM0, PWM2 and PWM4 are active-low
; LPOL = HIGH PWM0, PWM2 and PWM4 are active-high (default)
;
; PWM Output Pins Reset State Control bit:
; PWMPIN = ON PWM outputs drive active states upon Reset
; PWMPIN = OFF PWM outputs disabled upon Reset
;
; FLTA MUX bit:
; FLTAMX = RA7 FLTA input is muxed onto RA7
; FLTAMX = RA5 FLTA input is muxed onto RA5
;
; T1OSO/T1CKI MUX bit:
; T1OSCMX = LOW T1OSO/T1CKI pin resides on RB2
; T1OSCMX = HIGH T1OSO/T1CKI pin resides on RA6
;
; Master Clear Enable bit:
; MCLRE = OFF RA5 input pin enabled, MCLR pin disabled
; MCLRE = ON MCLR pin enabled, RA5 input pin disabled
;
; Stack Overflow/Underflow Reset Enable bit:
; STVREN = OFF Reset on stack overflow/underflow disabled
; STVREN = ON Reset on stack overflow/underflow enabled
;
; Boot Block Size Select bits:
; BBSIZ = BB256 256 Words (512 Bytes)
; BBSIZ = BB512 512 Words (1024 Bytes)
; BBSIZ = BB1K 1K Words (2048 Bytes)
;
; Extended Instruction Set Enable bit:
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
;
; Background Debugger Enable bit:
; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;
; Code Protection bit Block 0 (00800-00FFF):
; CP0 = ON Block 0 is code-protected
; CP0 = OFF Block 0 is not code-protected
;
; Code Protection bit Block 1 (01000-01FFF):
; CP1 = ON Block 1 is code-protected
; CP1 = OFF Block 1 is not code-protected
;
; Code Protection bit (Boot Block Memory Area):
; CPB = ON Boot Block is code-protected
; CPB = OFF Boot Block is not code-protected
;
; Code Protection bit (Data EEPROM):
; CPD = ON Data EEPROM is code-protected
; CPD = OFF Data EEPROM is not code-protected
;
; Write Protection bit Block 0 (00800-00FFF):
; WRT0 = ON Block 0 is write-protected
; WRT0 = OFF Block 0 is not write-protected
;
; Write Protection bit Block 1 (01000-01FFF):
; WRT1 = ON Block 1 is write-protected
; WRT1 = OFF Block 1 is not write-protected
;
; Write Protection bit (Boot Block Memory Area):
; WRTB = ON Boot Block is write-protected
; WRTB = OFF Boot Block is not write-protected
;
; Write Protection bit (Configuration Registers):
; WRTC = ON Configuration registers are write-protected
; WRTC = OFF Configuration registers are not write-protected
;
; Write Protection bit (Data EEPROM):
; WRTD = ON Data EEPROM is write-protected
; WRTD = OFF Data EEPROM is not write-protected
;
; Table Read Protection bit Block 0 (00800-00FFF):
; EBTR0 = ON Block 0 is protected from table reads executed in other blocks
; EBTR0 = OFF Block 0 is not protected from table reads executed in other blocks
;
; Table Read Protection bit Block 1 (01000-01FFF):
; EBTR1 = ON Block 1 is protected from table reads executed in other blocks
; EBTR1 = OFF Block 1 is not protected from table reads executed in other blocks
;
; Table Read Protection bit (Boot Block Memory Area):
; EBTRB = ON Boot Block is protected from table reads executed in other blocks
; EBTRB = OFF Boot Block is not protected from table reads executed in other blocks
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3L 300004h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
; CONFIG5H 300009h
; CONFIG6L 30000Ah
; CONFIG6H 30000Bh
; CONFIG7L 30000Ch
; CONFIG7H 30000Dh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3L EQU H'300004'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1H Options --------------------------------------------------
_OSC_LP_1H EQU H'F0' ; LP Oscillator
_OSC_XT_1H EQU H'F1' ; XT Oscillator
_OSC_HS_1H EQU H'F2' ; HS Oscillator
_OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6
_OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6
_OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6
_OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
_OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6
_OSC_INTIO2_1H EQU H'F8' ; Internal oscillator, port function on RA6 and RA7
_OSC_INTIO1_1H EQU H'F9' ; Internal oscillator, CLKO function on RA6, port function on RA7
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
_BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOR_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOR_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOR_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_0_2L EQU H'F3' ; Maximum setting
_BORV_1_2L EQU H'F7' ;
_BORV_2_2L EQU H'FB' ;
_BORV_3_2L EQU H'FF' ; Minimum setting
;----- CONFIG2H Options --------------------------------------------------
_WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit)
_WDT_ON_2H EQU H'FF' ; WDT enabled
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3L Options --------------------------------------------------
_HPOL_LOW_3L EQU H'F7' ; PWM1, PWM3 and PWM5 are active-low
_HPOL_HIGH_3L EQU H'FF' ; PWM1, PWM3 and PWM5 are active-high (default)
_LPOL_LOW_3L EQU H'FB' ; PWM0, PWM2 and PWM4 are active-low
_LPOL_HIGH_3L EQU H'FF' ; PWM0, PWM2 and PWM4 are active-high (default)
_PWMPIN_ON_3L EQU H'FD' ; PWM outputs drive active states upon Reset
_PWMPIN_OFF_3L EQU H'FF' ; PWM outputs disabled upon Reset
;----- CONFIG3H Options --------------------------------------------------
_FLTAMX_RA7_3H EQU H'FE' ; FLTA input is muxed onto RA7
_FLTAMX_RA5_3H EQU H'FF' ; FLTA input is muxed onto RA5
_T1OSCMX_LOW_3H EQU H'FF' ; T1OSO/T1CKI pin resides on RB2
_T1OSCMX_HIGH_3H EQU H'FF' ; T1OSO/T1CKI pin resides on RA6
_MCLRE_OFF_3H EQU H'7F' ; RA5 input pin enabled, MCLR pin disabled
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RA5 input pin disabled
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Reset on stack overflow/underflow disabled
_STVREN_ON_4L EQU H'FF' ; Reset on stack overflow/underflow enabled
_BBSIZ_BB256_4L EQU H'CF' ; 256 Words (512 Bytes)
_BBSIZ_BB512_4L EQU H'DF' ; 512 Words (1024 Bytes)
_BBSIZ_BB1K_4L EQU H'FF' ; 1K Words (2048 Bytes)
_XINST_OFF_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode disabled
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
_DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
_DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE' ; Block 0 is code-protected
_CP0_OFF_5L EQU H'FF' ; Block 0 is not code-protected
_CP1_ON_5L EQU H'FD' ; Block 1 is code-protected
_CP1_OFF_5L EQU H'FF' ; Block 1 is not code-protected
;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF' ; Boot Block is code-protected
_CPB_OFF_5H EQU H'FF' ; Boot Block is not code-protected
_CPD_ON_5H EQU H'7F' ; Data EEPROM is code-protected
_CPD_OFF_5H EQU H'FF' ; Data EEPROM is not code-protected
;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE' ; Block 0 is write-protected
_WRT0_OFF_6L EQU H'FF' ; Block 0 is not write-protected
_WRT1_ON_6L EQU H'FD' ; Block 1 is write-protected
_WRT1_OFF_6L EQU H'FF' ; Block 1 is not write-protected
;----- CONFIG6H Options --------------------------------------------------
_WRTB_ON_6H EQU H'BF' ; Boot Block is write-protected
_WRTB_OFF_6H EQU H'FF' ; Boot Block is not write-protected
_WRTC_ON_6H EQU H'DF' ; Configuration registers are write-protected
_WRTC_OFF_6H EQU H'FF' ; Configuration registers are not write-protected
_WRTD_ON_6H EQU H'7F' ; Data EEPROM is write-protected
_WRTD_OFF_6H EQU H'FF' ; Data EEPROM is not write-protected
;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE' ; Block 0 is protected from table reads executed in other blocks
_EBTR0_OFF_7L EQU H'FF' ; Block 0 is not protected from table reads executed in other blocks
_EBTR1_ON_7L EQU H'FD' ; Block 1 is protected from table reads executed in other blocks
_EBTR1_OFF_7L EQU H'FF' ; Block 1 is not protected from table reads executed in other blocks
;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF' ; Boot Block is protected from table reads executed in other blocks
_EBTRB_OFF_7H EQU H'FF' ; Boot Block is not protected from table reads executed in other blocks
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
LIST
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