📄 p18f14k50.inc
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; USB Clock Selection bit:
; USB_LSCLK = OFF USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide
; USB_LSCLK = ON USB clock comes from the OSC1/OSC2 divided by 2
;
; Oscillator Selection bits:
; FOSC = LP LP oscillator
; FOSC = XT XT oscillator
; FOSC = HS HS oscillator
; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2
; FOSC = ECCLKOUTh EC oscillator, CLKOUT function on OSC2 (high power)
; FOSC = ECh EC oscillator (high power)
; FOSC = ERC External RC oscillator
; FOSC = IRC Internal RC oscillator
; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2
; FOSC = ECCLKOUTm EC oscillator, CLKOUT function on OSC2 (medium power)
; FOSC = ECm EC oscillator (medium power)
; FOSC = ECCLKOUTl EC oscillator, CLKOUT function on OSC2 (low power)
; FOSC = ECl EC oscillator (low power)
;
; 4 X PLL Enable bit:
; PLL_EN = OFF Oscillator used directly
; PLL_EN = ON Oscillator multiplied by 4
;
; Primary Clock Enable Bit:
; PRI_CLK_EN = OFF Primary clock disabled
; PRI_CLK_EN = ON Primary clock enabled
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF Fail-Safe Clock Monitor disabled
; FCMEN = ON Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit:
; IESO = OFF Oscillator Switchover mode disabled
; IESO = ON Oscillator Switchover mode enabled
;
; Power-up Timer Enable bit:
; PWRT = ON PWRT enabled
; PWRT = OFF PWRT disabled
;
; Brown-out Reset Enable bits:
; BOREN = OFF Brown-out Reset disabled in hardware and software
; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
;
; Brown Out Voltage:
; BORV = 30 VBOR set to 3.0 V nominal
; BORV = 27 VBOR set to 2.7 V nominal
; BORV = 22 VBOR set to 2.2 V nominal
; BORV = 18 VBOR set to 1.8 V nominal
;
; Voltage Regulator Enable bit:
; VREGEN = OFF Voltage regulator is disabled/bypassed
; VREGEN = ON Voltage regulator is enabled
;
; BOR Power Enable bit:
; BORPWR = OFF Brown out reset configured for low power mode
; BORPWR = ON Brown out reset configured for high power mode
;
; Watchdog Timer Enable bit:
; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register
; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect.
;
; Watchdog Timer Postscale Select bits:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; MCLR Pin Enable bit:
; MCLRE = OFF RE3 input pin enabled; MCLR disabled
; MCLRE = ON MCLR pin enabled, RE3 input pin disabled
;
; HF-INTOSC Fast Startup:
; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable.
; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize.
;
; Stack Full/Underflow Reset Enable bit:
; STVREN = OFF Stack full/underflow will not cause Reset
; STVREN = ON Stack full/underflow will cause Reset
;
; Low Voltage Programming Enable bit:
; LVP = OFF Low Voltage Programming disabled
; LVP = ON Low Voltage Programming enabled
;
; Boot Block Size Select Bit:
; BBSIZ = OFF 1kW boot block size
; BBSIZ = ON 2kW boot block size
;
; Enhanced CPU enable bit:
; XINST = OFF Enhanced CPU disabled
; XINST = ON Enhanced CPU enabled
;
; Background Debugger Enable bit:
; BKBUG = ON Background debugger enabled
; BKBUG = OFF Background debugger disabled
;
; Code Protection Block 0:
; CP0 = ON Block 0 code-protected
; CP0 = OFF Block 0 not code-protected
;
; Code Protection Block 1:
; CP1 = ON Block 1 code-protected
; CP1 = OFF Block 1 not code-protected
;
; Boot Block Code Protection bit:
; CPB = ON Boot block code-protected
; CPB = OFF Boot block not code-protected
;
; Data EEPROM Code Protection bit:
; CPD = ON Data EEPROM code-protected
; CPD = OFF Data EEPROM not code-protected
;
; Write Protection Block 0:
; WRT0 = ON Block 0 write-protected
; WRT0 = OFF Block 0 not write-protected
;
; Write Protection Block 1:
; WRT1 = ON Block 1 write-protected
; WRT1 = OFF Block 1 not write-protected
;
; Boot Block Write Protection bit:
; WRTB = ON Boot block write-protected
; WRTB = OFF Boot block not write-protected
;
; Configuration Register Write Protection bit:
; WRTC = ON Configuration registers (300000-3000FFh) write-protected
; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
;
; Data EEPROM Write Protection bit:
; WRTD = ON Data EEPROM write-protected
; WRTD = OFF Data EEPROM not write-protected
;
; Table Read Protection Block 0:
; EBTR0 = ON Block 0 protected from table reads executed in other blocks
; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks
;
; Table Read Protection Block 1:
; EBTR1 = ON Block 1 protected from table reads executed in other blocks
; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks
;
; Boot Block Table Read Protection bit:
; EBTRB = ON Boot block protected from table reads executed in other blocks
; EBTRB = OFF Boot block not protected from table reads executed in other blocks
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1L 300000h
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
; CONFIG5H 300009h
; CONFIG6L 30000Ah
; CONFIG6H 30000Bh
; CONFIG7L 30000Ch
; CONFIG7H 30000Dh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1L EQU H'300000'
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1L Options --------------------------------------------------
_CPU_DIV_NoClkDiv_1L EQU H'E7' ; No CPU System Clock divide
_CPU_DIV_ClkDiv2_1L EQU H'EF' ; CPU System Clock divided by 2
_CPU_DIV_ClkDiv3_1L EQU H'F7' ; CPU System Clock divided by 3
_CPU_DIV_ClkDiv4_1L EQU H'FF' ; CPU System Clock divided by 4
_USB_LSCLK_OFF_1L EQU H'DF' ; USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide
_USB_LSCLK_ON_1L EQU H'FF' ; USB clock comes from the OSC1/OSC2 divided by 2
;----- CONFIG1H Options --------------------------------------------------
_FOSC_LP_1H EQU H'F0' ; LP oscillator
_FOSC_XT_1H EQU H'F1' ; XT oscillator
_FOSC_HS_1H EQU H'F2' ; HS oscillator
_FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2
_FOSC_ECCLKOUTh_1H EQU H'F4' ; EC oscillator, CLKOUT function on OSC2 (high power)
_FOSC_ECh_1H EQU H'F5' ; EC oscillator (high power)
_FOSC_ERC_1H EQU H'F7' ; External RC oscillator
_FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator
_FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2
_FOSC_ECCLKOUTm_1H EQU H'FA' ; EC oscillator, CLKOUT function on OSC2 (medium power)
_FOSC_ECm_1H EQU H'FB' ; EC oscillator (medium power)
_FOSC_ECCLKOUTl_1H EQU H'FC' ; EC oscillator, CLKOUT function on OSC2 (low power)
_FOSC_ECl_1H EQU H'FD' ; EC oscillator (low power)
_PLL_EN_OFF_1H EQU H'EF' ; Oscillator used directly
_PLL_EN_ON_1H EQU H'FF' ; Oscillator multiplied by 4
_PRI_CLK_EN_OFF_1H EQU H'DF' ; Primary clock disabled
_PRI_CLK_EN_ON_1H EQU H'FF' ; Primary clock enabled
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal
_BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal
_BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal
_BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal
_VREGEN_OFF_2L EQU H'DF' ; Voltage regulator is disabled/bypassed
_VREGEN_ON_2L EQU H'FF' ; Voltage regulator is enabled
_BORPWR_OFF_2L EQU H'BF' ; Brown out reset configured for low power mode
_BORPWR_ON_2L EQU H'FF' ; Brown out reset configured for high power mode
;----- CONFIG2H Options --------------------------------------------------
_WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register
_WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect.
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3H Options --------------------------------------------------
_MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled
_HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable.
_HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize.
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
_LVP_OFF_4L EQU H'FB' ; Low Voltage Programming disabled
_LVP_ON_4L EQU H'FF' ; Low Voltage Programming enabled
_BBSIZ_OFF_4L EQU H'F7' ; 1kW boot block size
_BBSIZ_ON_4L EQU H'FF' ; 2kW boot block size
_XINST_OFF_4L EQU H'BF' ; Enhanced CPU disabled
_XINST_ON_4L EQU H'FF' ; Enhanced CPU enabled
_BKBUG_ON_4L EQU H'7F' ; Background debugger enabled
_BKBUG_OFF_4L EQU H'FF' ; Background debugger disabled
;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE' ; Block 0 code-protected
_CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected
_CP1_ON_5L EQU H'FD' ; Block 1 code-protected
_CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected
;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF' ; Boot block code-protected
_CPB_OFF_5H EQU H'FF' ; Boot block not code-protected
_CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected
_CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected
;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE' ; Block 0 write-protected
_WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected
_WRT1_ON_6L EQU H'FD' ; Block 1 write-protected
_WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected
;----- CONFIG6H Options --------------------------------------------------
_WRTB_ON_6H EQU H'BF' ; Boot block write-protected
_WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected
_WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected
_WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected
_WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected
_WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected
;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks
_EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks
_EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks
_EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks
;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks
_EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
LIST
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