dff4.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
entity dff4 is
	port(clk,clr,d:in std_logic;
				q:out std_logic);
end dff4;
architecture rtl of dff4 is
begin 
	process(clk)
		begin
			if((clk'event) and (clk='1') )then
				if(clr='1') then
					q<='0';
				else
					q<=d;
				end if;
			end if;
	end process;
end rtl;