state_m2.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 60 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY state_m2 IS
PORT(clk, reset, nw : in std_logic;
	sel: out std_logic_vector(1 downto 0);
	nxt, first: out std_logic);
END state_m2;
ARCHITECTURE logic OF state_m2 IS
	TYPE state_type IS
	(idle, tap1, tap2, tap3, tap4);
	SIGNAL filter : state_type;
BEGIN
PROCESS (reset, clk)
BEGIN
	IF reset = '1' THEN
		filter <= idle;
	ELSIF clk'event and clk = '1' THEN
		CASE filter IS
			WHEN idle =>
				IF nw = '1' THEN
					filter <= tap1;
				END IF;
			WHEN tap1 =>
				filter <= tap2;
			WHEN tap2 =>
				filter <= tap3;
			WHEN tap3 =>
				filter <= tap4;
			WHEN tap4 =>
				IF nw = '1' THEN
					filter <= tap1;
				ELSE
					filter <= idle;
				END IF;
		END CASE;
	END IF;
END process;
output: PROCESS(filter)
BEGIN
	CASE filter IS
		WHEN idle =>
			nxt <= '0';
			first <= '0';
		WHEN tap1 =>
			sel <= "00";
			first <= '1';
		WHEN tap2 =>
			sel <= "01";
			first <= '0';
		WHEN tap3 =>
			sel <= "10";
		WHEN tap4 =>
			sel <= "11";
			nxt <= '1';
	END CASE;
END PROCESS output;
END logic;