tf.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 23 行

--tf
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity tf is
 port(clk:in std_logic;
       q,nq:out std_logic);
 end entity tf;
architecture rtl of tf is
 signal qn:std_logic:='0';--the initial value
begin
  q<=qn;
  nq<=not qn;
process(clk)
  begin
  if(clk'event and clk='0') then
   qn<=not qn;
  end if;
end process;
end rtl;