antishilver.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 20 行

--antishilver
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity antishilver is
  port(clk,sel,ajust,mode,ret:in std_logic;
       q1,q2,q3,q4:out std_logic);
end antishilver;
architecture behav of antishilver is
  begin
 process(clk,sel,ajust,mode,ret)
    begin
    if(clk'event and clk='0') then
       q1<=sel;q2<=ajust;q3<=mode;q4<=ret;
     end if;
    end process;
end behav;