division1.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 26 行

-- division1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity division1 is
port(	div_co	:	in	unsigned(9 downto 0);
	div_in	:	in	std_logic;
	div_out	:	out	std_logic);
end division1;
architecture division of division1 is
begin
	run : process
	variable counter : unsigned(9 downto 0);
	begin
		wait until div_in'event and div_in = '0';
		div_out <= '0';
		counter := counter + 1;
		if counter = div_co then
		div_out <= '1';
		counter := "0000000000";
		end if;
	end process;
end division;