decoding.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 32 行

-- decoding
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity decoding is
  port(sel:in std_logic_vector(1 downto 0);
         c:in std_logic;
       dec3,dec2,dec1,dec0:out std_logic);
 end decoding;

architecture rtl of decoding is
begin
process(sel)
begin
if(c='0') then
   dec3<='1';dec2<='1';dec1<='1';dec0<='0';
else
 if(sel="00") then
 dec3<='1';dec2<='1';dec1<='1';dec0<='0';
 elsif(sel="01") then
 dec3<='1';dec2<='1';dec1<='0';dec0<='1';
 elsif(sel="10") then
 dec3<='1';dec2<='0';dec1<='1';dec0<='1';
 elsif(sel="11") then
 dec3<='0';dec2<='1';dec1<='1';dec0<='1';
  end if;
end if; 
end process;
end rtl;