decoder1.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;

entity decoder1 is
port(cin:in std_logic_vector(7 downto 0);
     k1,k2:in std_logic;
     enad:out std_logic;
     ring:out std_logic
     );
end decoder1;     
     
architecture behav of decoder1 is
begin
process(cin,k1,k2)
begin
if cin="10101010" then
   ring<='0';
elsif cin="00110011" or k1='0' then
     enad<='0';
     ring<='1';
elsif k2='0' then
     enad<='1';
else ring<='1';           
end if;
end process;

end behav;