division1.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity division1 is
port(
       clk    :    in std_logic;
       clk4   :    out std_logic);
end division1;

architecture behave of division1 is
begin
     process(clk)
     variable counter : std_logic_vector(7 downto 0);
     begin
      if (clk'event and clk='0') then
        if (counter=250) then
           counter:="00000000";
           clk4<= '1';
        else
           counter:=counter+'1';
           clk4<='0';
        end if;
	  end if;
     end process;
end behave;