dynamic_digital.vhd

利用两个数码管

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity Dynamic_digital is
  port(
       clk: in  std_logic;
       wei :   out std_logic_vector(5 downto 0);
       duan:   out std_logic_vector(7 downto 0)
       );
end entity Dynamic_digital;

architecture lxf of Dynamic_digital is
signal clk1:  std_logic;
signal cnt1:   integer range 0 to 3000; --??
signal cnt2:   integer range 0 to 10000;
signal count1:   std_logic;
signal countge:   std_logic_vector(3 downto 0);
signal countshi:   std_logic_vector(3 downto 0);
signal yima:   std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk 'event and clk='1')then
 if(cnt1<1000)then cnt1<=cnt1+1;
 else 
	cnt1<=0;clk1<=not clk1;
  	count1<=not count1; 
end if;
end if;
end process;

process(clk1)
begin
if(clk1 'event and clk1='1')then
 if(cnt2<5000)then cnt2<=cnt2+1;
  else   cnt2<=0;
		if(countge<"1001") then
		countge<=countge+1;
		elsif (countshi<="1001") then
			countshi<=countshi+1;countge<="0000";
		else countshi<="0000";
		end if;
		
  end if;
end if;
end process;

process(count1,countge,countshi)
begin
case count1 is
	when '0' =>wei <= "000001"; yima<= countge;--1
	when '1' =>wei <= "000010";yima<= countshi;
    WHEN OTHERS =>wei <="000001";yima<= countge;
end case;
end process;	
process(yima)
begin
case yima is
	when "0000" =>duan <= "11000000";--0
	when "0001" =>duan <= "11111001";--1
	when "0010" =>duan <= "10100100";--2
	when "0011" =>duan <= "10110000";--3
	when "0100" =>duan <= "10011001";--4
	when "0101" =>duan <= "10010010";--5
	when "0110" =>duan <= "10000010";--6
	when "0111" =>duan <= "11111000";--7
	when "1000" =>duan <= "10000000";--8
	when "1001" =>duan <= "10010000";--9
    WHEN OTHERS =>duan <= "11000000";

end case;

end process;	  

end lxf;