static_digital.tan.rpt

来自「静态数码管显示的控制,数码管为共阳极数码管」· RPT 代码 · 共 377 行 · 第 1/5 页

; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[3] ; duan[2] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[0] ; duan[1] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[1] ; duan[1] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[2] ; duan[1] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[3] ; duan[1] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[0] ; duan[0] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[1] ; duan[0] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[2] ; duan[0] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[3] ; duan[0] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[0] ; duan[6] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[1] ; duan[6] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[2] ; duan[6] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[3] ; duan[6] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[0] ; duan[4] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[1] ; duan[4] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[2] ; duan[4] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[3] ; duan[4] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[0] ; duan[5] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[1] ; duan[5] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[2] ; duan[5] ; sysclk     ;
; N/A   ; None         ; 13.600 ns  ; lpm_counter:count_rtl_0|dffs[3] ; duan[5] ; sysclk     ;
+-------+--------------+------------+---------------------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Aug 12 11:19:35 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off static_digital -c static_digital
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "sysclk" is an undefined clock
Info: Clock "sysclk" has Internal fmax of 57.47 MHz between source register "cnt[0]" and destination register "cnt[8]" (period= 17.4 ns)
    Info: + Longest register to register delay is 12.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 38; REG Node = 'cnt[0]'
        Info: 2: + IC(2.800 ns) + CELL(4.400 ns) = 7.200 ns; Loc. = LC46; Fanout = 1; COMB Node = 'lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~8'
        Info: 3: + IC(2.600 ns) + CELL(3.100 ns) = 12.900 ns; Loc. = LC12; Fanout = 30; REG Node = 'cnt[8]'
        Info: Total cell delay = 7.500 ns ( 58.14 % )
        Info: Total interconnect delay = 5.400 ns ( 41.86 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "sysclk" to destination register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 29; CLK Node = 'sysclk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC12; Fanout = 30; REG Node = 'cnt[8]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
        Info: - Longest clock path from clock "sysclk" to source register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 29; CLK Node = 'sysclk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC1; Fanout = 38; REG Node = 'cnt[0]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tco from clock "sysclk" to destination pin "duan[3]" through register "lpm_counter:count_rtl_0|dffs[0]" is 13.600 ns
    Info: + Longest clock path from clock "sysclk" to source register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 29; CLK Node = 'sysclk'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC10; Fanout = 25; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 8.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 25; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
        Info: 2: + IC(2.600 ns) + CELL(4.400 ns) = 7.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'Mux3~156'
        Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.600 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'duan[3]'
        Info: Total cell delay = 6.000 ns ( 69.77 % )
        Info: Total interconnect delay = 2.600 ns ( 30.23 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Aug 12 11:19:35 2008
    Info: Elapsed time: 00:00:00