pwm.tan.qmsg

通过改变pwm的占空比

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 6 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:count1_rtl_2\|dffs\[7\] register lpm_counter:count1_rtl_2\|dffs\[4\] 88.5 MHz 11.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 88.5 MHz between source register \"lpm_counter:count1_rtl_2\|dffs\[7\]\" and destination register \"lpm_counter:count1_rtl_2\|dffs\[4\]\" (period= 11.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Longest register register " "Info: + Longest register to register delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count1_rtl_2\|dffs\[7\] 1 REG LC43 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC43; Fanout = 53; REG Node = 'lpm_counter:count1_rtl_2\|dffs\[7\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:count1_rtl_2|dffs[7] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.300 ns) 4.100 ns lpm_counter:count1_rtl_2\|dffs\[4\]~408 2 COMB LC51 1 " "Info: 2: + IC(2.800 ns) + CELL(1.300 ns) = 4.100 ns; Loc. = LC51; Fanout = 1; COMB Node = 'lpm_counter:count1_rtl_2\|dffs\[4\]~408'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { lpm_counter:count1_rtl_2|dffs[7] lpm_counter:count1_rtl_2|dffs[4]~408 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 6.800 ns lpm_counter:count1_rtl_2\|dffs\[4\] 3 REG LC52 31 " "Info: 3: + IC(0.000 ns) + CELL(2.700 ns) = 6.800 ns; Loc. = LC52; Fanout = 31; REG Node = 'lpm_counter:count1_rtl_2\|dffs\[4\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { lpm_counter:count1_rtl_2|dffs[4]~408 lpm_counter:count1_rtl_2|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 58.82 % ) " "Info: Total cell delay = 4.000 ns ( 58.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 41.18 % ) " "Info: Total interconnect delay = 2.800 ns ( 41.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.800 ns" { lpm_counter:count1_rtl_2|dffs[7] lpm_counter:count1_rtl_2|dffs[4]~408 lpm_counter:count1_rtl_2|dffs[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.800 ns" { lpm_counter:count1_rtl_2|dffs[7] lpm_counter:count1_rtl_2|dffs[4]~408 lpm_counter:count1_rtl_2|dffs[4] } { 0.000ns 2.800ns 0.000ns } { 0.000ns 1.300ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC27 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC27; Fanout = 17; REG Node = 'clk1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 10.000 ns lpm_counter:count1_rtl_2\|dffs\[4\] 3 REG LC52 31 " "Info: 3: + IC(2.800 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC52; Fanout = 31; REG Node = 'lpm_counter:count1_rtl_2\|dffs\[4\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.000 ns" { clk1 lpm_counter:count1_rtl_2|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total cell delay = 7.200 ns ( 72.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 28.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:count1_rtl_2|dffs[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:count1_rtl_2|dffs[4] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC27 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC27; Fanout = 17; REG Node = 'clk1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 10.000 ns lpm_counter:count1_rtl_2\|dffs\[7\] 3 REG LC43 53 " "Info: 3: + IC(2.800 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC43; Fanout = 53; REG Node = 'lpm_counter:count1_rtl_2\|dffs\[7\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.000 ns" { clk1 lpm_counter:count1_rtl_2|dffs[7] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total cell delay = 7.200 ns ( 72.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 28.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:count1_rtl_2|dffs[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:count1_rtl_2|dffs[7] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:count1_rtl_2|dffs[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:count1_rtl_2|dffs[4] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:count1_rtl_2|dffs[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:count1_rtl_2|dffs[7] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.800 ns" { lpm_counter:count1_rtl_2|dffs[7] lpm_counter:count1_rtl_2|dffs[4]~408 lpm_counter:count1_rtl_2|dffs[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.800 ns" { lpm_counter:count1_rtl_2|dffs[7] lpm_counter:count1_rtl_2|dffs[4]~408 lpm_counter:count1_rtl_2|dffs[4] } { 0.000ns 2.800ns 0.000ns } { 0.000ns 1.300ns 2.700ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:count1_rtl_2|dffs[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:count1_rtl_2|dffs[4] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:count1_rtl_2|dffs[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:count1_rtl_2|dffs[7] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q lpm_counter:v_rtl_1\|dffs\[1\] 31.000 ns register " "Info: tco from clock \"clk\" to destination pin \"q\" through register \"lpm_counter:v_rtl_1\|dffs\[1\]\" is 31.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC27 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC27; Fanout = 17; REG Node = 'clk1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 10.000 ns lpm_counter:v_rtl_1\|dffs\[1\] 3 REG LC10 28 " "Info: 3: + IC(2.800 ns) + CELL(2.200 ns) = 10.000 ns; Loc. = LC10; Fanout = 28; REG Node = 'lpm_counter:v_rtl_1\|dffs\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.000 ns" { clk1 lpm_counter:v_rtl_1|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total cell delay = 7.200 ns ( 72.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 28.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:v_rtl_1|dffs[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:v_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.400 ns + Longest register pin " "Info: + Longest register to pin delay is 19.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:v_rtl_1\|dffs\[1\] 1 REG LC10 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 28; REG Node = 'lpm_counter:v_rtl_1\|dffs\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:v_rtl_1|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.800 ns) 6.400 ns qq~444 2 COMB SEXP16 1 " "Info: 2: + IC(2.600 ns) + CELL(3.800 ns) = 6.400 ns; Loc. = SEXP16; Fanout = 1; COMB Node = 'qq~444'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.400 ns" { lpm_counter:v_rtl_1|dffs[1] qq~444 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 10.800 ns qq~450 3 COMB LC5 2 " "Info: 3: + IC(0.000 ns) + CELL(4.400 ns) = 10.800 ns; Loc. = LC5; Fanout = 2; COMB Node = 'qq~450'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { qq~444 qq~450 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.400 ns) 17.800 ns qq~456 4 COMB LC3 1 " "Info: 4: + IC(2.600 ns) + CELL(4.400 ns) = 17.800 ns; Loc. = LC3; Fanout = 1; COMB Node = 'qq~456'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { qq~450 qq~456 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 19.400 ns q 5 PIN PIN_1 0 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 19.400 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'q'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { qq~456 q } "NODE_NAME" } } { "pwm.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/4 pwm控制灯的亮暗/pwm/pwm.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.200 ns ( 73.20 % ) " "Info: Total cell delay = 14.200 ns ( 73.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 26.80 % ) " "Info: Total interconnect delay = 5.200 ns ( 26.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.400 ns" { lpm_counter:v_rtl_1|dffs[1] qq~444 qq~450 qq~456 q } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "19.400 ns" { lpm_counter:v_rtl_1|dffs[1] qq~444 qq~450 qq~456 q } { 0.000ns 2.600ns 0.000ns 2.600ns 0.000ns } { 0.000ns 3.800ns 4.400ns 4.400ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { clk clk1 lpm_counter:v_rtl_1|dffs[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { clk clk~out clk1 lpm_counter:v_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 2.800ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.400 ns" { lpm_counter:v_rtl_1|dffs[1] qq~444 qq~450 qq~456 q } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "19.400 ns" { lpm_counter:v_rtl_1|dffs[1] qq~444 qq~450 qq~456 q } { 0.000ns 2.600ns 0.000ns 2.600ns 0.000ns } { 0.000ns 3.800ns 4.400ns 4.400ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 21 20:23:32 2008 " "Info: Processing ended: Mon Apr 21 20:23:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}