📄 led.vhd
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library IEEE;--library used
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity led is--entity start
port( reset:in std_logic;
clk: in std_logic;
ledout: out std_logic_vector(7 downto 0)
);
end led;--end entity
architecture lxf of led is
signal count1 : std_logic_vector(2 DOWNTO 0); --start architecture lxf
begin
--process u1
u1:process(clk,reset)
variable count0:integer RANGE 20000000 DOWNTO 0;
begin
if (reset='1') then --reset pin assigned pin 89
if ( clk'event and clk = '1') then
count0 := count0 + 1;
if (count0 = 12000000) then --fen pin
count0 := 0;
count1<=count1+1;
end if ;
end if;
else count1<="000";
end if;
end process u1;
--process u1
u2:process (count1,clk)
begin
case count1 is
when "000" =>ledout <= "00000001";
when "001" =>ledout <= "00000010";
when "010" =>ledout <= "00000100";
when "011" =>ledout <= "00001000";
when "100" =>ledout <= "00010000";
when "101" =>ledout <= "00100000";
when "110" =>ledout <= "01000000";
when "111" =>ledout <= "10000000";
when others=>null;
end case;
end process u2 ;
end lxf;----end architecture lxf
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