led.drc.rpt

本实验完成发光二极管的循环点亮实验

; External reset should be correctly synchronized (R103)                                                                                                                                                                                                                           ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized (R104)                                                                                                                                         ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized (R105)                                                                                                                                                   ; On           ;
; Nodes with more than specified number of fan-outs (T101)                                                                                                                                                                                                                         ; On           ;
; Top nodes with highest fan-out (T102)                                                                                                                                                                                                                                            ; On           ;
; Design should not contain combinational loops (A101)                                                                                                                                                                                                                             ; On           ;
; Register output should not drive its own control signal directly or through combinational logic (A102)                                                                                                                                                                           ; On           ;
; Design should not contain delay chains (A103)                                                                                                                                                                                                                                    ; On           ;
; Design should not contain ripple clock structures (A104)                                                                                                                                                                                                                         ; On           ;
; Pulses should not be implemented asynchronously (A105)                                                                                                                                                                                                                           ; On           ;
; Multiple pulses should not be generated in design (A106)                                                                                                                                                                                                                         ; On           ;
; Design should not contain SR latches (A107)                                                                                                                                                                                                                                      ; On           ;
; Design should not contain latches (A108)                                                                                                                                                                                                                                         ; On           ;
; Combinational logic should not directly drive write enable signal of asynchronous RAM (A109)                                                                                                                                                                                     ; On           ;
; Design should not contain asynchronous memory (A110)                                                                                                                                                                                                                             ; On           ;
; Output enable and input of same tri-state node should not be driven by same signal source (S101)                                                                                                                                                                                 ; On           ;
; Synchronous port and reset port of same register should not be driven by same signal source (S102)                                                                                                                                                                               ; On           ;
; Data bits are not synchronized when transferred between asynchronous clock domains (D101)                                                                                                                                                                                        ; On           ;
; Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in receiving clock domain (D102)                                                                                                                     ; On           ;
; Data bits are not correctly synchronized when transferred between asynchronous clock domains (D103)                                                                                                                                                                              ; On           ;
; Only one VREF pin should be assigned to HardCopy test pin in an I/O bank (H101) (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On           ;
; PLL drives multiple clock network types (H102) (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.)                                  ; On           ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+


+----------------------------------------------------------+
; Information only Violations                              ;
+---------------------------------------+--------+---------+
; Rule name                             ; Name   ; Fan-Out ;
+---------------------------------------+--------+---------+
; Top nodes with highest fan-out (T102) ; ~GND~0 ; 1       ;
; Top nodes with highest fan-out (T102) ; ~GND~1 ; 1       ;
; Top nodes with highest fan-out (T102) ; ~GND~2 ; 1       ;
; Top nodes with highest fan-out (T102) ; ~GND~3 ; 1       ;
; Top nodes with highest fan-out (T102) ; ~GND~4 ; 1       ;
; Top nodes with highest fan-out (T102) ; ~GND~5 ; 1       ;
; Top nodes with highest fan-out (T102) ; ~GND~6 ; 1       ;
; Top nodes with highest fan-out (T102) ; ~GND~7 ; 1       ;
+---------------------------------------+--------+---------+


+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Design Assistant
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Mar 24 10:20:55 2008
Info: Command: quartus_drc --read_settings_files=on --write_settings_files=off led -c led
Info: Design Assistant information: Top nodes with highest fan-out (T102). Found 8 node(s) with highest fan-out.
    Info: Node "~GND~0" has 1 fan-out(s)
    Info: Node "~GND~1" has 1 fan-out(s)
    Info: Node "~GND~2" has 1 fan-out(s)
    Info: Node "~GND~3" has 1 fan-out(s)
    Info: Node "~GND~4" has 1 fan-out(s)
    Info: Node "~GND~5" has 1 fan-out(s)
    Info: Node "~GND~6" has 1 fan-out(s)
    Info: Node "~GND~7" has 1 fan-out(s)
Info: Design Assistant information: finished post-fitting analysis of current design -- generated 8 information messages and 0 warning messages
Info: Quartus II Design Assistant was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Mar 24 10:20:55 2008
    Info: Elapsed time: 00:00:01