led.drc.rpt

本实验完成发光二极管的循环点亮实验

Design Assistant report for led
Mon Mar 24 10:20:55 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Design Assistant Summary
  3. Design Assistant Settings
  4. Information only Violations
  5. Design Assistant Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Design Assistant Summary                                                ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status           ; Analyzed - Mon Mar 24 10:20:55 2008 ;
; Revision Name                     ; led                                 ;
; Top-level Entity Name             ; led                                 ;
; Family                            ; MAX3000A                            ;
; Total Critical Violations         ; 0                                   ;
; Total High Violations             ; 0                                   ;
; Total Medium Violations           ; 0                                   ;
; Total Information only Violations ; 8                                   ;
+-----------------------------------+-------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Option                                                                                                                                                                                                                                                                           ; Setting      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Design Assistant mode                                                                                                                                                                                                                                                            ; Post-Fitting ;
; Threshold value for clock net not mapped to clock spines rule                                                                                                                                                                                                                    ; 25           ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                   ; 30           ;
; Maximum number of nodes to report                                                                                                                                                                                                                                                ; 50           ;
; Gated clock should be implemented according to Altera standard scheme (C101)                                                                                                                                                                                                     ; On           ;
; Logic cell should not be used to generate inverted clock (C102)                                                                                                                                                                                                                  ; On           ;
; Input clock pin should fan out to only one set of clock gating logic (C103)                                                                                                                                                                                                      ; On           ;
; Clock signal source should drive only input clock ports (C104)                                                                                                                                                                                                                   ; On           ;
; Clock signal should be a global signal (C105) (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On           ;
; Clock signal source should not drive registers that are triggered by different clock edges (C106)                                                                                                                                                                                ; On           ;
; Combinational logic used as reset signal should be synchronized (R101)                                                                                                                                                                                                           ; On           ;
; External reset should be synchronized using two cascaded registers (R102)                                                                                                                                                                                                        ; On           ;