📄 led.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register comb~31 register comb~17 82.64 MHz 12.1 ns Internal " "Info: Clock \"clk\" has Internal fmax of 82.64 MHz between source register \"comb~31\" and destination register \"comb~17\" (period= 12.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register register " "Info: + Longest register to register delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns comb~31 1 REG LC36 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 23; REG Node = 'comb~31'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { comb~31 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 4.000 ns count0~167 2 COMB LC4 1 " "Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 4.000 ns; Loc. = LC4; Fanout = 1; COMB Node = 'count0~167'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { comb~31 count0~167 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.900 ns count0~169 3 COMB LC5 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.900 ns; Loc. = LC5; Fanout = 1; COMB Node = 'count0~169'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { count0~167 count0~169 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 7.600 ns comb~17 4 REG LC6 37 " "Info: 4: + IC(0.000 ns) + CELL(2.700 ns) = 7.600 ns; Loc. = LC6; Fanout = 37; REG Node = 'comb~17'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { count0~169 comb~17 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns ( 64.47 % ) " "Info: Total cell delay = 4.900 ns ( 64.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 35.53 % ) " "Info: Total interconnect delay = 2.700 ns ( 35.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.600 ns" { comb~31 count0~167 count0~169 comb~17 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.600 ns" { comb~31 count0~167 count0~169 comb~17 } { 0.000ns 2.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns comb~17 2 REG LC6 37 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC6; Fanout = 37; REG Node = 'comb~17'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk comb~17 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~17 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~17 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns comb~31 2 REG LC36 23 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC36; Fanout = 23; REG Node = 'comb~31'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk comb~31 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~31 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~31 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~17 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~17 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~31 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~31 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.600 ns" { comb~31 count0~167 count0~169 comb~17 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.600 ns" { comb~31 count0~167 count0~169 comb~17 } { 0.000ns 2.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 2.700ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~17 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~17 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~31 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~31 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "comb~1 reset clk 4.900 ns register " "Info: tsu for register \"comb~1\" (data pin = \"reset\", clock pin = \"clk\") is 4.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.400 ns + Longest pin register " "Info: + Longest pin to register delay is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 28; PIN Node = 'reset'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.300 ns) 5.400 ns comb~1 2 REG LC34 38 " "Info: 2: + IC(1.600 ns) + CELL(1.300 ns) = 5.400 ns; Loc. = LC34; Fanout = 38; REG Node = 'comb~1'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { reset comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 70.37 % ) " "Info: Total cell delay = 3.800 ns ( 70.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 29.63 % ) " "Info: Total interconnect delay = 1.600 ns ( 29.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { reset comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { reset reset~out comb~1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.500ns 1.300ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns comb~1 2 REG LC34 38 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC34; Fanout = 38; REG Node = 'comb~1'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~1 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { reset comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { reset reset~out comb~1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.500ns 1.300ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~1 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk ledout\[7\] count1\[0\] 13.700 ns register " "Info: tco from clock \"clk\" to destination pin \"ledout\[7\]\" through register \"count1\[0\]\" is 13.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns count1\[0\] 2 REG LC2 11 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 11; REG Node = 'count1\[0\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk count1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk count1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count1[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest register pin " "Info: + Longest register to pin delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[0\] 1 REG LC2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'count1\[0\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 7.100 ns Mux7~106 2 COMB LC22 1 " "Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 7.100 ns; Loc. = LC22; Fanout = 1; COMB Node = 'Mux7~106'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.100 ns" { count1[0] Mux7~106 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 8.700 ns ledout\[7\] 3 PIN PIN_10 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.700 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'ledout\[7\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { Mux7~106 ledout[7] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 68.97 % ) " "Info: Total cell delay = 6.000 ns ( 68.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 31.03 % ) " "Info: Total interconnect delay = 2.700 ns ( 31.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.700 ns" { count1[0] Mux7~106 ledout[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.700 ns" { count1[0] Mux7~106 ledout[7] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk count1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count1[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.700 ns" { count1[0] Mux7~106 ledout[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.700 ns" { count1[0] Mux7~106 ledout[7] } { 0.000ns 2.700ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "comb~1 reset clk -0.700 ns register " "Info: th for register \"comb~1\" (data pin = \"reset\", clock pin = \"clk\") is -0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns comb~1 2 REG LC34 38 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC34; Fanout = 38; REG Node = 'comb~1'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~1 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 28 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 28; PIN Node = 'reset'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "led.vhd" "" { Text "E:/epm3128开发学习板/基于quartus的学习开发板试验系统（vhdl编程）/实验代码部分/1跑马灯/led/led.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.300 ns) 5.400 ns comb~1 2 REG LC34 38 " "Info: 2: + IC(1.600 ns) + CELL(1.300 ns) = 5.400 ns; Loc. = LC34; Fanout = 38; REG Node = 'comb~1'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { reset comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 70.37 % ) " "Info: Total cell delay = 3.800 ns ( 70.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 29.63 % ) " "Info: Total interconnect delay = 1.600 ns ( 29.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { reset comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { reset reset~out comb~1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.500ns 1.300ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out comb~1 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { reset comb~1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { reset reset~out comb~1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.500ns 1.300ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 21 19:51:41 2008 " "Info: Processing ended: Mon Apr 21 19:51:41 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -