led.tan.rpt

本实验完成发光二极管的循环点亮实验

+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+-------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To      ; To Clock ;
+---------------+-------------+-----------+-------+---------+----------+
; N/A           ; None        ; -0.700 ns ; reset ; comb~1  ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~15 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~13 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~11 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~9  ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~7  ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~5  ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~3  ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~31 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~29 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~27 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~25 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~47 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~21 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~19 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~23 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~45 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~43 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~39 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~37 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~35 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~33 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~17 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~41 ; clk      ;
; N/A           ; None        ; -0.700 ns ; reset ; comb~49 ; clk      ;
+---------------+-------------+-----------+-------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Apr 21 19:51:41 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 82.64 MHz between source register "comb~31" and destination register "comb~17" (period= 12.1 ns)
    Info: + Longest register to register delay is 7.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 23; REG Node = 'comb~31'
        Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 4.000 ns; Loc. = LC4; Fanout = 1; COMB Node = 'count0~167'
        Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.900 ns; Loc. = LC5; Fanout = 1; COMB Node = 'count0~169'
        Info: 4: + IC(0.000 ns) + CELL(2.700 ns) = 7.600 ns; Loc. = LC6; Fanout = 37; REG Node = 'comb~17'
        Info: Total cell delay = 4.900 ns ( 64.47 % )
        Info: Total interconnect delay = 2.700 ns ( 35.53 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC6; Fanout = 37; REG Node = 'comb~17'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC36; Fanout = 23; REG Node = 'comb~31'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "comb~1" (data pin = "reset", clock pin = "clk") is 4.900 ns
    Info: + Longest pin to register delay is 5.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 28; PIN Node = 'reset'
        Info: 2: + IC(1.600 ns) + CELL(1.300 ns) = 5.400 ns; Loc. = LC34; Fanout = 38; REG Node = 'comb~1'
        Info: Total cell delay = 3.800 ns ( 70.37 % )
        Info: Total interconnect delay = 1.600 ns ( 29.63 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC34; Fanout = 38; REG Node = 'comb~1'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "ledout[7]" through register "count1[0]" is 13.700 ns
    Info: + Longest clock path from clock "clk" to source register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 28; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 11; REG Node = 'count1[0]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 8.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'count1[0]'
        Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 7.100 ns; Loc. = LC22; Fanout = 1; COMB Node = 'Mux7~106'
        Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.700 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'ledout[7]'
        Info: Total cell delay = 6.