📄 arm1176jzf-s.h
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#ifndef __ARM1176JZF-S_H__
#define __ARM1176JZF-S_H__
/*
*********************************************************************************************************
* CORE MODULE REGISTERS
*********************************************************************************************************
*/
/* Control registers */
#define CM_ID (*(volatile CPU_INT32U *)(0x10000000))
#define CM_PROC (*(volatile CPU_INT32U *)(0x10000004))
#define CM_OSC (*(volatile CPU_INT32U *)(0x10000008))
#define CM_CTRL (*(volatile CPU_INT32U *)(0x1000000C))
#define CM_STAT (*(volatile CPU_INT32U *)(0x10000010))
#define CM_LOCK (*(volatile CPU_INT32U *)(0x10000014))
#define CM_LMBUSCNT (*(volatile CPU_INT32U *)(0x10000018))
#define CM_AUXOSC (*(volatile CPU_INT32U *)(0x1000001C))
#define CM_SDRAM (*(volatile CPU_INT32U *)(0x10000020))
#define CM_INIT (*(volatile CPU_INT32U *)(0x10000024))
#define CM_REFCT (*(volatile CPU_INT32U *)(0x10000028))
#define CM_UNUSED1 (*(volatile CPU_INT32U *)(0x1000002C))
/* Flag registers */
#define CM_FLAGS (*(volatile CPU_INT32U *)(0x10000030))
#define CM_FLAGSS (*(volatile CPU_INT32U *)(0x10000030))
#define CM_FLAGSC (*(volatile CPU_INT32U *)(0x10000034))
#define CM_NVFLAGS (*(volatile CPU_INT32U *)(0x10000038))
#define CM_NVFLAGSS (*(volatile CPU_INT32U *)(0x10000038))
#define CM_NVFLAGSC (*(volatile CPU_INT32U *)(0x1000003C))
/* Interrupt registers */
#define CM_IRQ_STAT (*(volatile CPU_INT32U *)(0x10000040))
#define CM_IRQ_RSTAT (*(volatile CPU_INT32U *)(0x10000044))
#define CM_IRQ_ENSET (*(volatile CPU_INT32U *)(0x10000048))
#define CM_IRQ_ENCLR (*(volatile CPU_INT32U *)(0x1000004C))
#define CM_SOFT_INTSET (*(volatile CPU_INT32U *)(0x10000050))
#define CM_SOFT_INTCLR (*(volatile CPU_INT32U *)(0x10000054))
#define CM_FIQ_STAT (*(volatile CPU_INT32U *)(0x10000060))
#define CM_FIQ_RSTAT (*(volatile CPU_INT32U *)(0x10000064))
#define CM_FIQ_ENSET (*(volatile CPU_INT32U *)(0x10000068))
#define CM_FIQ_ENCLR (*(volatile CPU_INT32U *)(0x1000006C))
/* Voltage registers */
#define CM_VOLTAGE_CTL0 (*(volatile CPU_INT32U *)(0x10000080))
#define CM_VOLTAGE_CLT1 (*(volatile CPU_INT32U *)(0x10000084))
#define CM_VOLTAGE_CLT2 (*(volatile CPU_INT32U *)(0x10000088))
#define CM_VOLTAGE_CTL3 (*(volatile CPU_INT32U *)(0x1000008C))
/* Serial Presence Detect Memory */
#define CM_SPD(x) (*(volatile CPU_INT32U *)(0x10000100 + 4 * (x)))
/*
*********************************************************************************************************
* COUNTER/TIMER REGISTERS
*********************************************************************************************************
*/
#define TIMER0_LOAD (*(volatile CPU_INT32U *)(0x13000000))
#define TIMER0_VALUE (*(volatile CPU_INT32U *)(0x13000004))
#define TIMER0_CONTROL (*(volatile CPU_INT32U *)(0x13000008))
#define TIMER0_INTCLR (*(volatile CPU_INT32U *)(0x1300000C))
#define TIMER0_RIS (*(volatile CPU_INT32U *)(0x13000010))
#define TIMER0_MIS (*(volatile CPU_INT32U *)(0x13000014))
#define TIMER0_BGLOAD (*(volatile CPU_INT32U *)(0x13000018))
#define TIMER1_LOAD (*(volatile CPU_INT32U *)(0x13000100))
#define TIMER1_VALUE (*(volatile CPU_INT32U *)(0x13000104))
#define TIMER1_CONTROL (*(volatile CPU_INT32U *)(0x13000108))
#define TIMER1_INTCLR (*(volatile CPU_INT32U *)(0x1300010C))
#define TIMER1_RIS (*(volatile CPU_INT32U *)(0x13000110))
#define TIMER1_MIS (*(volatile CPU_INT32U *)(0x13000114))
#define TIMER1_BGLOAD (*(volatile CPU_INT32U *)(0x13000118))
#define TIMER2_LOAD (*(volatile CPU_INT32U *)(0x13000200))
#define TIMER2_VALUE (*(volatile CPU_INT32U *)(0x13000204))
#define TIMER2_CONTROL (*(volatile CPU_INT32U *)(0x13000208))
#define TIMER2_INTCLR (*(volatile CPU_INT32U *)(0x1300020C))
#define TIMER2_RIS (*(volatile CPU_INT32U *)(0x13000210))
#define TIMER2_MIS (*(volatile CPU_INT32U *)(0x13000214))
#define TIMER2_BGLOAD (*(volatile CPU_INT32U *)(0x13000218))
#define TIMER_CONTROL_ENABLE ((CPU_INT32U) (0x00000080))
#define TIMER_CONTROL_FREERUNNING ((CPU_INT32U) (0x00000000))
#define TIMER_CONTROL_PERIODIC ((CPU_INT32U) (0x00000040))
#define TIMER_CONTROL_IE ((CPU_INT32U) (0x00000020))
#define TIMER_CONTROL_PRESCALE_NONE ((CPU_INT32U) (0x00000000))
#define TIMER_CONTROL_PRESCALE_16 ((CPU_INT32U) (0x00000004))
#define TIMER_CONTROL_PRESCALE_256 ((CPU_INT32U) (0x00000008))
#define TIMER_CONTROL_SIZE_16BIT ((CPU_INT32U) (0x00000000))
#define TIMER_CONTROL_SIZE_32BIT ((CPU_INT32U) (0x00000002))
#define TIMER_CONTROL_WRAPPING ((CPU_INT32U) (0x00000000))
#define TIMER_CONTROL_ONESHOT ((CPU_INT32U) (0x00000001))
/*
*********************************************************************************************************
* PRIMARY INTERRUPT REGISTERS
*********************************************************************************************************
*/
#define PIC_IRQ_STATUS (*(volatile CPU_INT32U *)(0x14000000))
#define PIC_IRQ_RAWSTAT (*(volatile CPU_INT32U *)(0x14000004))
#define PIC_IRQ_ENABLESET (*(volatile CPU_INT32U *)(0x14000008))
#define PIC_IRQ_ENABLECLR (*(volatile CPU_INT32U *)(0x1400000C))
#define PIC_INT_SOFTSET (*(volatile CPU_INT32U *)(0x14000010))
#define PIC_INT_SOFTCLR (*(volatile CPU_INT32U *)(0x14000014))
#define PIC_FIQ_STATUS (*(volatile CPU_INT32U *)(0x14000020))
#define PIC_FIQ_RAWSTAT (*(volatile CPU_INT32U *)(0x14000024))
#define PIC_FIQ_ENABLESET (*(volatile CPU_INT32U *)(0x14000028))
#define PIC_FIQ_ENABLECLR (*(volatile CPU_INT32U *)(0x1400002C))
#define PIC_IRQ_TS_PENINT ((CPU_INT32U) (0x10000000))
#define PIC_IRQ_ETH_INT ((CPU_INT32U) (0x08000000))
#define PIC_IRQ_CPPLDINT ((CPU_INT32U) (0x04000000))
#define PIC_IRQ_AACIINT ((CPU_INT32U) (0x02000000))
#define PIC_IRQ_MMCIINT1 ((CPU_INT32U) (0x01000000))
#define PIC_IRQ_MMCIINT0 ((CPU_INT32U) (0x00800000))
#define PIC_IRQ_CLCDINT ((CPU_INT32U) (0x00400000))
#define PIC_IRQ_LM_LLINT1 ((CPU_INT32U) (0x00000400))
#define PIC_IRQ_LM_LLINT0 ((CPU_INT32U) (0x00000200))
#define PIC_IRQ_RTCINT ((CPU_INT32U) (0x00000100))
#define PIC_IRQ_TIMERINT2 ((CPU_INT32U) (0x00000080))
#define PIC_IRQ_TIMERINT1 ((CPU_INT32U) (0x00000040))
#define PIC_IRQ_TIMERINT0 ((CPU_INT32U) (0x00000020))
#define PIC_IRQ_MOUSEINT ((CPU_INT32U) (0x00000010))
#define PIC_IRQ_KBDINT ((CPU_INT32U) (0x00000008))
#define PIC_IRQ_UARTINT1 ((CPU_INT32U) (0x00000004))
#define PIC_IRQ_UARTINT0 ((CPU_INT32U) (0x00000002))
#define PIC_IRQ_SOFTINT ((CPU_INT32U) (0x00000001))
#define PIC_TS_PENINT ((CPU_INT08U) (28))
#define PIC_ETH_INT ((CPU_INT08U) (27))
#define PIC_CPPLDINT ((CPU_INT08U) (26))
#define PIC_AACIINT ((CPU_INT08U) (25))
#define PIC_MMCIINT1 ((CPU_INT08U) (24))
#define PIC_MMCIINT0 ((CPU_INT08U) (23))
#define PIC_CLCDINT ((CPU_INT08U) (22))
#define PIC_LM_LLINT1 ((CPU_INT08U) (10))
#define PIC_LM_LLINT0 ((CPU_INT08U) (9))
#define PIC_RTCINT ((CPU_INT08U) (8))
#define PIC_TIMERINT2 ((CPU_INT08U) (7))
#define PIC_TIMERINT1 ((CPU_INT08U) (6))
#define PIC_TIMERINT0 ((CPU_INT08U) (5))
#define PIC_MOUSEINT ((CPU_INT08U) (4))
#define PIC_KBDINT ((CPU_INT08U) (3))
#define PIC_UARTINT1 ((CPU_INT08U) (2))
#define PIC_UARTINT0 ((CPU_INT08U) (1))
#define PIC_SOFTINT ((CPU_INT08U) (0))
/*
*********************************************************************************************************
* REAL-TIME CLOCK REGISTERS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* UART0 REGISTERS
*********************************************************************************************************
*/
#define UART0_DR (*(volatile CPU_INT32U *)(0x16000000))
#define UART0_SR (*(volatile CPU_INT32U *)(0x16000004))
#define UART0_FR (*(volatile CPU_INT32U *)(0x16000018))
#define UART0_ILPR (*(volatile CPU_INT32U *)(0x16000020))
#define UART0_IBRD (*(volatile CPU_INT32U *)(0x16000024))
#define UART0_FBRD (*(volatile CPU_INT32U *)(0x16000028))
#define UART0_LCR_H (*(volatile CPU_INT32U *)(0x1600002C))
#define UART0_CR (*(volatile CPU_INT32U *)(0x16000030))
#define UART0_IFLS (*(volatile CPU_INT32U *)(0x16000034))
#define UART0_IMSC (*(volatile CPU_INT32U *)(0x16000038))
#define UART0_RIS (*(volatile CPU_INT32U *)(0x1600003C))
#define UART0_MIS (*(volatile CPU_INT32U *)(0x16000040))
#define UART0_ICR (*(volatile CPU_INT32U *)(0x16000044))
#define UART0_DMACR (*(volatile CPU_INT32U *)(0x16000048))
#define UART0_PERIPHID0 (*(volatile CPU_INT32U *)(0x16000FE0))
#define UART0_PERIPHID1 (*(volatile CPU_INT32U *)(0x16000FE4))
#define UART0_PERIPHID2 (*(volatile CPU_INT32U *)(0x16000FE8))
#define UART0_PERIPHID3 (*(volatile CPU_INT32U *)(0x16000FEC))
#define UART0_PCELLID0 (*(volatile CPU_INT32U *)(0x16000FF0))
#define UART0_PCELLID1 (*(volatile CPU_INT32U *)(0x16000FF4))
#define UART0_PCELLID2 (*(volatile CPU_INT32U *)(0x16000FF8))
#define UART0_PCELLID3 (*(volatile CPU_INT32U *)(0x16000FFC))
/*
*********************************************************************************************************
* UART1 REGISTERS
*********************************************************************************************************
*/
#define UART1_DR (*(volatile CPU_INT32U *)(0x17000000))
#define UART1_SR (*(volatile CPU_INT32U *)(0x17000004))
#define UART1_FR (*(volatile CPU_INT32U *)(0x17000018))
#define UART1_ILPR (*(volatile CPU_INT32U *)(0x17000020))
#define UART1_IBRD (*(volatile CPU_INT32U *)(0x17000024))
#define UART1_FBRD (*(volatile CPU_INT32U *)(0x17000028))
#define UART1_LCR_H (*(volatile CPU_INT32U *)(0x1700002C))
#define UART1_CR (*(volatile CPU_INT32U *)(0x17000030))
#define UART1_IFLS (*(volatile CPU_INT32U *)(0x17000034))
#define UART1_IMSC (*(volatile CPU_INT32U *)(0x17000038))
#define UART1_RIS (*(volatile CPU_INT32U *)(0x1700003C))
#define UART1_MIS (*(volatile CPU_INT32U *)(0x17000040))
#define UART1_ICR (*(volatile CPU_INT32U *)(0x17000044))
#define UART1_DMACR (*(volatile CPU_INT32U *)(0x17000048))
#define UART1_PERIPHID0 (*(volatile CPU_INT32U *)(0x17000FE0))
#define UART1_PERIPHID1 (*(volatile CPU_INT32U *)(0x17000FE4))
#define UART1_PERIPHID2 (*(volatile CPU_INT32U *)(0x17000FE8))
#define UART1_PERIPHID3 (*(volatile CPU_INT32U *)(0x17000FEC))
#define UART1_PCELLID0 (*(volatile CPU_INT32U *)(0x17000FF0))
#define UART1_PCELLID1 (*(volatile CPU_INT32U *)(0x17000FF4))
#define UART1_PCELLID2 (*(volatile CPU_INT32U *)(0x17000FF8))
#define UART1_PCELLID3 (*(volatile CPU_INT32U *)(0x17000FFC))
/*
*********************************************************************************************************
* KEYBOARD REGISTERS
*********************************************************************************************************
*/
#define KMI1_CR (*(volatile CPU_INT32U *)(0x18000000))
#define KMI1_STAT (*(volatile CPU_INT32U *)(0x18000004))
#define KMI1_DATA (*(volatile CPU_INT32U *)(0x18000008))
#define KMI1_IR (*(volatile CPU_INT32U *)(0x18000010))
/*
*********************************************************************************************************
* MOUSE REGISTERS
*********************************************************************************************************
*/
#define KMI2_CR (*(volatile CPU_INT32U *)(0x19000000))
#define KMI2_STAT (*(volatile CPU_INT32U *)(0x19000004))
#define KMI2_DATA (*(volatile CPU_INT32U *)(0x19000008))
#define KMI2_IR (*(volatile CPU_INT32U *)(0x19000010))
/*
*********************************************************************************************************
* DEBUG LED & DIP SWITCH REGISTERS
*********************************************************************************************************
*/
#define LED_ALPHA (*(volatile CPU_INT32U *)(0x1A000000))
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