📄 wangjin-schematic1-wangjin.out
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**** 12/14/06 12:02:04 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-wangjin" [ D:\EDA_PROJECT\ORCAD\wangjin\wangjin-schematic1-wangjin.sim ]
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "wangjin-schematic1-wangjin.sim.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of d:\eda\orcad\PSpice\PSpice.ini file:
.lib "nom.lib"
*Analysis directives:
.TRAN 0 100ms 0 100us
.PROBE V(*) I(*) W(*) D(*) NOISE(*)
.INC ".\wangjin-SCHEMATIC1.net"
**** INCLUDING wangjin-SCHEMATIC1.net ****
* source WANGJIN
C_C2 0 N05849 0.01uf
X_U1A VCC N05603 N05401 $G_CD4000_VDD $G_CD4000_VSS CD4093B PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
V_V1 VCC 0
+PWL 0 0 1ns 5v
X_U2A N05401 N05849 N05919 $G_CD4000_VDD $G_CD4000_VSS CD4093B PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R2 N05849 N05919 50k
C_C1 0 N05603 .1uf
R_R1 N05603 N05401 100k
**** RESUMING wangjin-schematic1-wangjin.sim.cir ****
.END
**** Generated AtoD and DtoA Interfaces ****
*
* Analog/Digital interface for node N05849
*
* Moving X_U2A.UJ:IN2 from analog node N05849 to new digital node N05849$AtoD
X$N05849_AtoD1
+ N05849
+ N05849$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B_ST
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node VCC
*
* Moving X_U1A.UJ:IN1 from analog node VCC to new digital node VCC$AtoD
X$VCC_AtoD1
+ VCC
+ VCC$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B_ST
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node N05919
*
* Moving X_U2A.UJ:OUT1 from analog node N05919 to new digital node N05919$DtoA
X$N05919_DtoA1
+ N05919$DtoA
+ N05919
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ DtoA_4000B
+ PARAMS: DRVH= 1.4430E+03 DRVL= 1.4430E+03 CAPACITANCE= 0
*
* Analog/Digital interface for node N05603
*
* Moving X_U1A.UJ:IN2 from analog node N05603 to new digital node N05603$AtoD
X$N05603_AtoD1
+ N05603
+ N05603$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B_ST
+ PARAMS: CAPACITANCE= 0
*
* Analog/Digital interface for node N05401
*
* Moving X_U2A.UJ:IN1 from analog node N05401 to new digital node N05401$AtoD
X$N05401_AtoD1
+ N05401
+ N05401$AtoD
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ AtoD_4000B_ST
+ PARAMS: CAPACITANCE= 0
* Moving X_U1A.UJ:OUT1 from analog node N05401 to new digital node N05401$DtoA
X$N05401_DtoA1
+ N05401$DtoA
+ N05401
+ $G_CD4000_VDD
+ $G_CD4000_VSS
+ DtoA_4000B
+ PARAMS: DRVH= 1.4430E+03 DRVL= 1.4430E+03 CAPACITANCE= 0
*
* Analog/Digital interface power supply subcircuits
*
X$CD4000_PWR 0 CD4000_PWR
**** 12/14/06 12:02:04 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-wangjin" [ D:\EDA_PROJECT\ORCAD\wangjin\wangjin-schematic1-wangjin.sim ]
**** Diode MODEL PARAMETERS
******************************************************************************
D74CLMP
IS 1.000000E-15
RS 2
CJO 2.000000E-12
**** 12/14/06 12:02:04 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-wangjin" [ D:\EDA_PROJECT\ORCAD\wangjin\wangjin-schematic1-wangjin.sim ]
**** Digital Input MODEL PARAMETERS
******************************************************************************
DIN4000B
FILE DSO_DTOA
FORMAT 6
TIMESTEP 100.000000E-12
S0NAME 0
S0TSW 15.000000E-09
S0RLO 1
S0RHI 80.000000E+03
S1NAME 1
S1TSW 15.000000E-09
S1RLO 40.000000E+03
S1RHI 1
S2NAME X
S2TSW 15.000000E-09
S2RLO 800
S2RHI 800
S3NAME R
S3TSW 15.000000E-09
S3RLO 800
S3RHI 800
S4NAME F
S4TSW 15.000000E-09
S4RLO 800
S4RHI 800
S5NAME Z
S5TSW 15.000000E-09
S5RLO 1.000000E+06
S5RHI 1.000000E+06
**** 12/14/06 12:02:04 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-wangjin" [ D:\EDA_PROJECT\ORCAD\wangjin\wangjin-schematic1-wangjin.sim ]
**** Digital Output MODEL PARAMETERS
******************************************************************************
DO4000B_ST
FILE DSO_ATOD
FORMAT 6
CHGONLY 1
TIMESTEP 100.000000E-12
S0NAME 0
S0VHI .2
S0VLO -3
S1NAME 1
S1VHI 3
S1VLO -.3
**** 12/14/06 12:02:04 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-wangjin" [ D:\EDA_PROJECT\ORCAD\wangjin\wangjin-schematic1-wangjin.sim ]
**** Digital Gate MODEL PARAMETERS
******************************************************************************
D_CD4093B
TPLHMN 76.000000E-09
TPLHTY 190.000000E-09
TPLHMX 380.000000E-09
TPHLMN 76.000000E-09
TPHLTY 190.000000E-09
TPHLMX 380.000000E-09
**** 12/14/06 12:02:04 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-wangjin" [ D:\EDA_PROJECT\ORCAD\wangjin\wangjin-schematic1-wangjin.sim ]
**** Digital IO MODEL PARAMETERS
******************************************************************************
IO_4000B_ST IO_4000B
DRVL 1.443000E+03 1.443000E+03
DRVH 1.443000E+03 1.443000E+03
AtoD1 AtoD_4000B_ST AtoD_4000B
AtoD2 AtoD_4000B_ST AtoD_4000B_NX
AtoD3 AtoD_4000B_ST AtoD_4000B
AtoD4 AtoD_4000B_ST AtoD_4000B_NX
DtoA1 DtoA_4000B DtoA_4000B
DtoA2 DtoA_4000B DtoA_4000B
DtoA3 DtoA_4000B DtoA_4000B
DtoA4 DtoA_4000B DtoA_4000B
DIGPOWER CD4000_PWR CD4000_PWR
TSWHL1 7.720000E-09 7.720000E-09
TSWHL2 7.860000E-09 7.860000E-09
TSWHL3 9.710000E-09 9.710000E-09
TSWHL4 9.630000E-09 9.630000E-09
TSWLH1 7.560000E-09 7.560000E-09
TSWLH2 7.400000E-09 7.400000E-09
TSWLH3 9.410000E-09 9.410000E-09
TSWLH4 9.240000E-09 9.240000E-09
TPWRT 100.000000E+03 100.000000E+03
WARNING -- X$N05919_DtoA1.N1 forced to X state for bias point
WARNING -- X$N05919_DtoA1.N1 forced to X state for bias point
WARNING -- X$N05919_DtoA1.N1 forced to X state for bias point
WARNING -- X$N05919_DtoA1.N1 forced to X state for bias point
WARNING -- Unable to converge all DtoA interface devices
**** 12/14/06 12:02:04 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-wangjin" [ D:\EDA_PROJECT\ORCAD\wangjin\wangjin-schematic1-wangjin.sim ]
**** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C
******************************************************************************
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( VCC)-444.1E-18 (N05401) 4.9391 (N05603) 4.9342 (N05849) 2.6504
(N05919) 2.6506 ($G_CD4000_VDD) 5.0000
($G_CD4000_VSS) 0.0000 (X$VCC_AtoD1.NORM) -1.2500
(X$N05401_AtoD1.NORM) 1.2196 (X$N05603_AtoD1.NORM) 1.2171
(X$N05849_AtoD1.NORM) .0752 (X$N05401_DtoA1.DRVGND) .0810
(X$N05401_DtoA1.DRVPWR) 4.9392 (X$N05919_DtoA1.DRVGND) 1.2048
(X$N05919_DtoA1.DRVPWR) 4.0964 (X$N05401_DtoA1.X1.DRVN) .0015
(X$N05401_DtoA1.X1.DRVP) .0020 (X$N05919_DtoA1.X1.DRVN) .0015
(X$N05919_DtoA1.X1.DRVP) .0020 (X$VCC_AtoD1.XNORM.THRESHOLD) 1.5000
(X$N05401_AtoD1.XNORM.THRESHOLD) 1.5000
(X$N05603_AtoD1.XNORM.THRESHOLD) 1.5000
(X$N05849_AtoD1.XNORM.THRESHOLD) 1.5000
DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE
(N05849$AtoD) : 0 (N05919$DtoA) : 1 (N05603$AtoD) : 1 (N05401$AtoD) : 1
(VCC$AtoD) : 0 (N05401$DtoA) : 1
VOLTAGE SOURCE CURRENTS
NAME CURRENT
V_V1 5.001E-08
X$CD4000_PWR.VVDD -1.934E-03
X$CD4000_PWR.VVSS -5.050E-06
TOTAL POWER DISSIPATION 9.67E-03 WATTS
JOB CONCLUDED
TOTAL JOB TIME 5.70
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