📄 msp430x24x_wdt_04.s43
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;*******************************************************************************
; MSP430x24x Demo - WDT+ Failsafe Clock, DCO SMCLK
;
; Description; Allow WDT+ in watchdog to timeout. Toggle P1.0 in main
; function. LPM4 is entered, this example will demonstrate WDT+ feature
; of preventing WDT+ clock to be disabled.
; The WDT+ will not allow active WDT+ clock to be disabled by software, the
; LED continues to Flash because the WDT times out normally even though
; software has attempted to disable WDT+ clock source.
; ACLK = n/a, MCLK = SMCLK = default DCO ~1.045MHz
;
; MSP430F249
; -----------------
; /|\| XIN|-
; | | |
; --|RST XOUT|-
; | |
; | P1.0|-->LED
;
; B. Nisarga
; Texas Instruments Inc.
; September 2007
; Built with IAR Embedded Workbench Version: 3.42A
;*******************************************************************************
#include "msp430x24x.h"
;-------------------------------------------------------------------------------
RSEG CSTACK ; Define stack segment
;-------------------------------------------------------------------------------
RSEG CODE ; Assemble to Flash memory
;-------------------------------------------------------------------------------
RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
SetupP1 bis.b #001h,&P1DIR ; P1.0 output
xor.b #001h,&P1OUT ; Toggle P1.0
Mainloop bis.w #LPM4+GIE,SR ; Disable all clocks
nop ;
;-------------------------------------------------------------------------------
COMMON INTVEC ; Interrupt Vectors
;-------------------------------------------------------------------------------
ORG RESET_VECTOR ; MSP430 RESET Vector
DW RESET ;
END
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