songer.map.qmsg

首先将核心板插在我们的EDA底板4.0上面,然后将板上的跳线J20 EXT_SEL跳到ON,也就是插上. 1。源文件保存在src目录

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 25 23:33:15 2005 " "Info: Processing started: Mon Jul 25 23:33:15 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off music -c songer " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off music -c songer" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TONETABA.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file TONETABA.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ToneTaba-one " "Info: Found design unit 1: ToneTaba-one" {  } { { "D:/ep1c12V3/music/TONETABA.VHD" "ToneTaba-one" "" { Text "D:/ep1c12V3/music/TONETABA.VHD" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ToneTaba " "Info: Found entity 1: ToneTaba" {  } { { "D:/ep1c12V3/music/TONETABA.VHD" "ToneTaba" "" { Text "D:/ep1c12V3/music/TONETABA.VHD" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NOTETABS.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file NOTETABS.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NoteTabs-one " "Info: Found design unit 1: NoteTabs-one" {  } { { "D:/ep1c12V3/music/NOTETABS.VHD" "NoteTabs-one" "" { Text "D:/ep1c12V3/music/NOTETABS.VHD" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 NoteTabs " "Info: Found entity 1: NoteTabs" {  } { { "D:/ep1c12V3/music/NOTETABS.VHD" "NoteTabs" "" { Text "D:/ep1c12V3/music/NOTETABS.VHD" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SPEAKERA.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file SPEAKERA.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Speakera-one " "Info: Found design unit 1: Speakera-one" {  } { { "D:/ep1c12V3/music/SPEAKERA.VHD" "Speakera-one" "" { Text "D:/ep1c12V3/music/SPEAKERA.VHD" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Speakera " "Info: Found entity 1: Speakera" {  } { { "D:/ep1c12V3/music/SPEAKERA.VHD" "Speakera" "" { Text "D:/ep1c12V3/music/SPEAKERA.VHD" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "Songer.vhd 2 1 " "Info: Using design file Songer.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Songer-one " "Info: Found design unit 1: Songer-one" {  } { { "D:/ep1c12V3/music/Songer.vhd" "Songer-one" "" { Text "D:/ep1c12V3/music/Songer.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Songer " "Info: Found entity 1: Songer" {  } { { "D:/ep1c12V3/music/Songer.vhd" "Songer" "" { Text "D:/ep1c12V3/music/Songer.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter NOTETABS.VHD(12) " "Warning: VHDL Process Statement warning at NOTETABS.VHD(12): signal counter is in statement, but is not in sensitivity list" {  } { { "d:/ep1c6/music/NOTETABS.VHD" "" "" { Text "d:/ep1c6/music/NOTETABS.VHD" 12 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "NOTETABS.VHD(175) " "Info: VHDL Case Statement information at NOTETABS.VHD(175): OTHERS choice is never selected" {  } { { "d:/ep1c6/music/NOTETABS.VHD" "" "" { Text "d:/ep1c6/music/NOTETABS.VHD" 175 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "tone TONETABA.VHD(11) " "Warning: VHDL Process Statement warning at TONETABA.VHD(11): signal or variable tone may not be assigned a new value in every possible path through the Process Statement. Signal or variable tone holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "d:/ep1c6/music/TONETABA.VHD" "" "" { Text "d:/ep1c6/music/TONETABA.VHD" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "code TONETABA.VHD(11) " "Warning: VHDL Process Statement warning at TONETABA.VHD(11): signal or variable code may not be assigned a new value in every possible path through the Process Statement. Signal or variable code holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "d:/ep1c6/music/TONETABA.VHD" "" "" { Text "d:/ep1c6/music/TONETABA.VHD" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "high TONETABA.VHD(11) " "Warning: VHDL Process Statement warning at TONETABA.VHD(11): signal or variable high may not be assigned a new value in every possible path through the Process Statement. Signal or variable high holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "d:/ep1c6/music/TONETABA.VHD" "" "" { Text "d:/ep1c6/music/TONETABA.VHD" 11 0 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "16 " "Info: Ignored 16 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "16 " "Info: Ignored 16 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Speakera:u3\|SpkS Speakera:u3\|\\DelaySpkS:Count2 " "Info: Duplicate register Speakera:u3\|SpkS merged to single register Speakera:u3\|\\DelaySpkS:Count2" {  } { { "d:/ep1c6/music/SPEAKERA.VHD" "" "" { Text "d:/ep1c6/music/SPEAKERA.VHD" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speakera:u3\|\\GenSpkS:Count11\[0\]~0 11 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: Speakera:u3\|\\GenSpkS:Count11\[0\]~0" {  } {  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "Speakera:u3\|\\DivideCLK:Count4\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: Speakera:u3\|\\DivideCLK:Count4\[0\]~0" {  } {  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "NoteTabs:u1\|Counter\[0\]~0 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: NoteTabs:u1\|Counter\[0\]~0" {  } { { "d:/ep1c6/music/NOTETABS.VHD" "" "Counter\[0\]~0" { Text "d:/ep1c6/music/NOTETABS.VHD" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/alt_counter_stratix.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/alt_counter_stratix.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_stratix " "Info: Found entity 1: alt_counter_stratix" {  } { { "c:/altera/quartus41/libraries/megafunctions/alt_counter_stratix.tdf" "alt_counter_stratix" "" { Text "c:/altera/quartus41/libraries/megafunctions/alt_counter_stratix.tdf" 282 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "CODE1\[3\] GND " "Warning: Pin CODE1\[3\] stuck at GND" {  } { { "d:/ep1c6/music/songer.vhd" "" "" { Text "d:/ep1c6/music/songer.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "121 " "Info: Implemented 121 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "113 " "Info: Implemented 113 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 25 23:33:24 2005 " "Info: Processing ended: Mon Jul 25 23:33:24 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}