songer.tan.rpt

首先将核心板插在我们的EDA底板4.0上面,然后将板上的跳线J20 EXT_SEL跳到ON,也就是插上. 1。源文件保存在src目录

; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                    ;
+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                                         ; To                                                                                           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 19.955 ns                                      ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[1]             ; CODE1[2]                                                                                     ; CLK8HZ     ;          ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 10.758 ns                                      ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[3]             ; CODE1[1]                                                                                     ; CLK8HZ     ;          ; 0            ;
; Clock Setup: 'CLK12MHZ'      ; N/A   ; None          ; 190.15 MHz ( period = 5.259 ns )               ; Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] ; Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2] ; CLK12MHZ   ; CLK12MHZ ; 0            ;
; Clock Setup: 'CLK8HZ'        ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[1]             ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[5]             ; CLK8HZ     ; CLK8HZ   ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                              ;                                                                                              ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK8HZ          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; CLK12MHZ        ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK8HZ'                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                             ; To                                                                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[1] ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[7] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[1] ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[6] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[1] ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[5] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[0] ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[7] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[0] ; NoteTabs:u1|lpm_counter:Counter_rtl_2|alt_counter_stratix:wysi_counter|safe_q[6] ; CLK8HZ     ; CLK8HZ   ; None                        ; None                      ; None                    ;