proj.tan.qmsg

首先将核心板插在EDA底板4.0上面,然后将板上的跳线J20 EXT_SEL跳到ON,也就是插上. 1。源文件保存在src目录

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[2\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[15\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[0\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[1\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[5\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[6\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[6\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[3\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[4\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[9\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[9\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[10\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[10\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[7\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[7\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[8\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[8\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[14\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[14\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[11\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[11\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~385 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~385\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~385" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~382 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~382\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~382" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~384 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~384\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~384" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~383 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~383\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~383" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[12\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[12\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div16:inst1\|count\[3\] " "Info: Detected ripple clock \"div16:inst1\|count\[3\]\" as buffer" {  } { { "../src/div16.v" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/div16.v" 5 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div16:inst1\|count\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[13\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[13\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkdiv " "Info: Detected ripple clock \"lcd:inst\|clkdiv\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 75 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkdiv" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clk_int " "Info: Detected ripple clock \"lcd:inst\|clk_int\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 71 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clk_int" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:inst\|counter\[5\] register lcd:inst\|state\[9\] 103.39 MHz 9.672 ns Internal " "Info: Clock \"clk\" has Internal fmax of 103.39 MHz between source register \"lcd:inst\|counter\[5\]\" and destination register \"lcd:inst\|state\[9\]\" (period= 9.672 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.170 ns + Longest register register " "Info: + Longest register to register delay is 7.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[5\] 1 REG LC_X49_Y20_N6 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X49_Y20_N6; Fanout = 12; REG Node = 'lcd:inst\|counter\[5\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "" { lcd:inst|counter[5] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.330 ns) + CELL(0.590 ns) 1.920 ns lcd:inst\|LessThan~390 2 COMB LC_X50_Y21_N3 2 " "Info: 2: + IC(1.330 ns) + CELL(0.590 ns) = 1.920 ns; Loc. = LC_X50_Y21_N3; Fanout = 2; COMB Node = 'lcd:inst\|LessThan~390'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.920 ns" { lcd:inst|counter[5] lcd:inst|LessThan~390 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.114 ns) 3.554 ns lcd:inst\|LessThan~391 3 COMB LC_X49_Y20_N8 3 " "Info: 3: + IC(1.520 ns) + CELL(0.114 ns) = 3.554 ns; Loc. = LC_X49_Y20_N8; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~391'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.634 ns" { lcd:inst|LessThan~390 lcd:inst|LessThan~391 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.227 ns) + CELL(0.590 ns) 5.371 ns lcd:inst\|char_addr~1489 4 COMB LC_X49_Y21_N9 3 " "Info: 4: + IC(1.227 ns) + CELL(0.590 ns) = 5.371 ns; Loc. = LC_X49_Y21_N9; Fanout = 3; COMB Node = 'lcd:inst\|char_addr~1489'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.817 ns" { lcd:inst|LessThan~391 lcd:inst|char_addr~1489 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.607 ns) 7.170 ns lcd:inst\|state\[9\] 5 REG LC_X49_Y22_N7 5 " "Info: 5: + IC(1.192 ns) + CELL(0.607 ns) = 7.170 ns; Loc. = LC_X49_Y22_N7; Fanout = 5; REG Node = 'lcd:inst\|state\[9\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.799 ns" { lcd:inst|char_addr~1489 lcd:inst|state[9] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.901 ns 26.51 % " "Info: Total cell delay = 1.901 ns ( 26.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.269 ns 73.49 % " "Info: Total interconnect delay = 5.269 ns ( 73.49 % )" {  } {  } 0}  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "7.170 ns" { lcd:inst|counter[5] lcd:inst|LessThan~390 lcd:inst|LessThan~391 lcd:inst|char_addr~1489 lcd:inst|state[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.170 ns" { lcd:inst|counter[5] lcd:inst|LessThan~390 lcd:inst|LessThan~391 lcd:inst|char_addr~1489 lcd:inst|state[9] } { 0.000ns 1.330ns 1.520ns 1.227ns 1.192ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.241 ns - Smallest " "Info: - Smallest clock skew is -2.241 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 20.288 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 20.288 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div16:inst1\|count\[3\] 2 REG LC_X8_Y13_N4 17 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N4; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.965 ns" { clk div16:inst1|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.935 ns) 7.942 ns lcd:inst\|clkcnt\[2\] 3 REG LC_X9_Y12_N6 3 " "Info: 3: + IC(3.573 ns) + CELL(0.935 ns) = 7.942 ns; Loc. = LC_X9_Y12_N6; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[2\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "4.508 ns" { div16:inst1|count[3] lcd:inst|clkcnt[2] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 8.320 ns lcd:inst\|reduce_nor~385 4 COMB LC_X9_Y12_N6 1 " "Info: 4: + IC(0.000 ns) + CELL(0.378 ns) = 8.320 ns; Loc. = LC_X9_Y12_N6; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~385'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "0.378 ns" { lcd:inst|clkcnt[2] lcd:inst|reduce_nor~385 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.114 ns) 8.860 ns lcd:inst\|reduce_nor~386 5 COMB LC_X9_Y12_N9 7 " "Info: 5: + IC(0.426 ns) + CELL(0.114 ns) = 8.860 ns; Loc. = LC_X9_Y12_N9; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~386'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "0.540 ns" { lcd:inst|reduce_nor~385 lcd:inst|reduce_nor~386 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.935 ns) 10.562 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N1 3 " "Info: 6: + IC(0.767 ns) + CELL(0.935 ns) = 10.562 ns; Loc. = LC_X8_Y12_N1; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.702 ns" { lcd:inst|reduce_nor~386 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.145 ns) + CELL(0.935 ns) 15.642 ns lcd:inst\|clk_int 7 REG LC_X9_Y13_N2 20 " "Info: 7: + IC(4.145 ns) + CELL(0.935 ns) = 15.642 ns; Loc. = LC_X9_Y13_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "5.080 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.935 ns) + CELL(0.711 ns) 20.288 ns lcd:inst\|state\[9\] 8 REG LC_X49_Y22_N7 5 " "Info: 8: + IC(3.935 ns) + CELL(0.711 ns) = 20.288 ns; Loc. = LC_X49_Y22_N7; Fanout = 5; REG Node = 'lcd:inst\|state\[9\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "4.646 ns" { lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.412 ns 31.60 % " "Info: Total cell delay = 6.412 ns ( 31.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.876 ns 68.40 % " "Info: Total interconnect delay = 13.876 ns ( 68.40 % )" {  } {  } 0}  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "20.288 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~385 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "20.288 ns" { clk clk~out0 div16:inst1|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~385 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } { 0.000ns 0.000ns 1.030ns 3.573ns 0.000ns 0.426ns 0.767ns 4.145ns 3.935ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 22.529 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 22.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div16:inst1\|count\[3\] 2 REG LC_X8_Y13_N4 17 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N4; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.965 ns" { clk div16:inst1|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.935 ns) 7.942 ns lcd:inst\|clkcnt\[8\] 3 REG LC_X8_Y11_N9 4 " "Info: 3: + IC(3.573 ns) + CELL(0.935 ns) = 7.942 ns; Loc. = LC_X8_Y11_N9; Fanout = 4; REG Node = 'lcd:inst\|clkcnt\[8\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "4.508 ns" { div16:inst1|count[3] lcd:inst|clkcnt[8] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.590 ns) 9.803 ns lcd:inst\|reduce_nor~383 4 COMB LC_X9_Y12_N5 1 " "Info: 4: + IC(1.271 ns) + CELL(0.590 ns) = 9.803 ns; Loc. = LC_X9_Y12_N5; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~383'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.861 ns" { lcd:inst|clkcnt[8] lcd:inst|reduce_nor~383 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.590 ns) 11.101 ns lcd:inst\|reduce_nor~386 5 COMB LC_X9_Y12_N9 7 " "Info: 5: + IC(0.708 ns) + CELL(0.590 ns) = 11.101 ns; Loc. = LC_X9_Y12_N9; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~386'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.298 ns" { lcd:inst|reduce_nor~383 lcd:inst|reduce_nor~386 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.935 ns) 12.803 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N1 3 " "Info: 6: + IC(0.767 ns) + CELL(0.935 ns) = 12.803 ns; Loc. = LC_X8_Y12_N1; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.702 ns" { lcd:inst|reduce_nor~386 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.145 ns) + CELL(0.935 ns) 17.883 ns lcd:inst\|clk_int 7 REG LC_X9_Y13_N2 20 " "Info: 7: + IC(4.145 ns) + CELL(0.935 ns) = 17.883 ns; Loc. = LC_X9_Y13_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "5.080 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.935 ns) + CELL(0.711 ns) 22.529 ns lcd:inst\|counter\[5\] 8 REG LC_X49_Y20_N6 12 " "Info: 8: + IC(3.935 ns) + CELL(0.711 ns) = 22.529 ns; Loc. = LC_X49_Y20_N6; Fanout = 12; REG Node = 'lcd:inst\|counter\[5\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "4.646 ns" { lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 31.51 % " "Info: Total cell delay = 7.100 ns ( 31.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.429 ns 68.49 % " "Info: Total interconnect delay = 15.429 ns ( 68.49 % )" {  } {  } 0}  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "22.529 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[8] lcd:inst|reduce_nor~383 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.529 ns" { clk clk~out0 div16:inst1|count[3] lcd:inst|clkcnt[8] lcd:inst|reduce_nor~383 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } { 0.000ns 0.000ns 1.030ns 3.573ns 1.271ns 0.708ns 0.767ns 4.145ns 3.935ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "20.288 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~385 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "20.288 ns" { clk clk~out0 div16:inst1|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~385 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } { 0.000ns 0.000ns 1.030ns 3.573ns 0.000ns 0.426ns 0.767ns 4.145ns 3.935ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "22.529 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[8] lcd:inst|reduce_nor~383 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.529 ns" { clk clk~out0 div16:inst1|count[3] lcd:inst|clkcnt[8] lcd:inst|reduce_nor~383 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } { 0.000ns 0.000ns 1.030ns 3.573ns 1.271ns 0.708ns 0.767ns 4.145ns 3.935ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 56 -1 0 } }  } 0}  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "7.170 ns" { lcd:inst|counter[5] lcd:inst|LessThan~390 lcd:inst|LessThan~391 lcd:inst|char_addr~1489 lcd:inst|state[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.170 ns" { lcd:inst|counter[5] lcd:inst|LessThan~390 lcd:inst|LessThan~391 lcd:inst|char_addr~1489 lcd:inst|state[9] } { 0.000ns 1.330ns 1.520ns 1.227ns 1.192ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.607ns } } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "20.288 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~385 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "20.288 ns" { clk clk~out0 div16:inst1|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~385 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } { 0.000ns 0.000ns 1.030ns 3.573ns 0.000ns 0.426ns 0.767ns 4.145ns 3.935ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "22.529 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[8] lcd:inst|reduce_nor~383 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.529 ns" { clk clk~out0 div16:inst1|count[3] lcd:inst|clkcnt[8] lcd:inst|reduce_nor~383 lcd:inst|reduce_nor~386 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } { 0.000ns 0.000ns 1.030ns 3.573ns 1.271ns 0.708ns 0.767ns 4.145ns 3.935ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.935ns 0.935ns 0.711ns } } }  } 0}