proj.fit.qmsg

首先将核心板插在EDA底板4.0上面,然后将板上的跳线J20 EXT_SEL跳到ON,也就是插上. 1。源文件保存在src目录

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.726 ns register register " "Info: Estimated most critical path is register to register delay of 5.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[3\] 1 REG LAB_X49_Y20 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X49_Y20; Fanout = 14; REG Node = 'lcd:inst\|counter\[3\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "" { lcd:inst|counter[3] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(0.292 ns) 1.442 ns lcd:inst\|LessThan~390 2 COMB LAB_X50_Y21 2 " "Info: 2: + IC(1.150 ns) + CELL(0.292 ns) = 1.442 ns; Loc. = LAB_X50_Y21; Fanout = 2; COMB Node = 'lcd:inst\|LessThan~390'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.442 ns" { lcd:inst|counter[3] lcd:inst|LessThan~390 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.074 ns) + CELL(0.292 ns) 2.808 ns lcd:inst\|LessThan~391 3 COMB LAB_X49_Y20 3 " "Info: 3: + IC(1.074 ns) + CELL(0.292 ns) = 2.808 ns; Loc. = LAB_X49_Y20; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~391'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.366 ns" { lcd:inst|LessThan~390 lcd:inst|LessThan~391 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.442 ns) 4.174 ns lcd:inst\|char_addr~1489 4 COMB LAB_X49_Y21 3 " "Info: 4: + IC(0.924 ns) + CELL(0.442 ns) = 4.174 ns; Loc. = LAB_X49_Y21; Fanout = 3; COMB Node = 'lcd:inst\|char_addr~1489'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.366 ns" { lcd:inst|LessThan~391 lcd:inst|char_addr~1489 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.074 ns) + CELL(0.478 ns) 5.726 ns lcd:inst\|state\[9\] 5 REG LAB_X49_Y22 5 " "Info: 5: + IC(1.074 ns) + CELL(0.478 ns) = 5.726 ns; Loc. = LAB_X49_Y22; Fanout = 5; REG Node = 'lcd:inst\|state\[9\]'" {  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "1.552 ns" { lcd:inst|char_addr~1489 lcd:inst|state[9] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.504 ns 26.27 % " "Info: Total cell delay = 1.504 ns ( 26.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.222 ns 73.73 % " "Info: Total interconnect delay = 4.222 ns ( 73.73 % )" {  } {  } 0}  } { { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "5.726 ns" { lcd:inst|counter[3] lcd:inst|LessThan~390 lcd:inst|LessThan~391 lcd:inst|char_addr~1489 lcd:inst|state[9] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "KEYS2/AD_CS VCC " "Info: Pin KEYS2/AD_CS has VCC driving its datain port" {  } { { "lcd_test.bdf" "" { Schematic "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/lcd_test.bdf" { { 432 568 744 448 "KEYS2/AD_CS" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KEYS2/AD_CS" } } } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "" { KEYS2/AD_CS } "NODE_NAME" } "" } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/Proj.fld" "" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/Proj.fld" "" "" { KEYS2/AD_CS } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "KEYS1/USB_CS VCC " "Info: Pin KEYS1/USB_CS has VCC driving its datain port" {  } { { "lcd_test.bdf" "" { Schematic "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/lcd_test.bdf" { { 456 568 745 472 "KEYS1/USB_CS" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KEYS1/USB_CS" } } } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "" { KEYS1/USB_CS } "NODE_NAME" } "" } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/Proj.fld" "" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/Proj.fld" "" "" { KEYS1/USB_CS } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "KEYS3/U11_CS GND " "Info: Pin KEYS3/U11_CS has GND driving its datain port" {  } { { "lcd_test.bdf" "" { Schematic "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/lcd_test.bdf" { { 480 568 745 496 "KEYS3/U11_CS" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KEYS3/U11_CS" } } } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/" "" "" { KEYS3/U11_CS } "NODE_NAME" } "" } } { "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/Proj.fld" "" { Floorplan "E:/EDA/HSNIOSV4.0/EDA4.0底板程序/LCD1602/Proj/Proj.fld" "" "" { KEYS3/U11_CS } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 24 22:25:56 2006 " "Info: Processing ended: Mon Jul 24 22:25:56 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}