binary.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 34 行

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity BINARY is

      Port (   clk : In    std_logic;
             reset : In    std_logic;
             count : BUFFER UNSIGNED (3 downto 0));
end BINARY;

architecture BEHAVIORAL of BINARY is
	begin
	process(reset,clk,count)
	begin
	if (reset = '0') then
		count <= "0000";
	elsif (clk'event and clk = '1')then
		if (count = UNSIGNED'("1111")) then
			count <= "0000";
		else
			count <= count + UNSIGNED'("1");
		end if;
	end if;
	end process;
end BEHAVIORAL;

configuration CFG_BINARY_BLOCK_BEHAVIORAL of BINARY is
	for BEHAVIORAL

	end for;

end CFG_BINARY_BLOCK_BEHAVIORAL;