hal_cache.h

ecos下的gui开发源代码

#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H

//=============================================================================
//
//      hal_cache.h
//
//      HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   whhhh
// Contributors:        nickg
// Date:        2007-07-27
// Purpose:     Cache control API
// Description: The macros defined here provide the HAL APIs for handling
//              cache control operations.
// Usage:
//              #include <cyg/hal/hal_cache.h>
//              ...
//              
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
//#include <cyg/hal/plf_cache.h>


externC void cyg_start( void ); 


//=============================================================================
// Default Implementation. This uses the standard SCORE CR4 registers and
// cache instructions. Note that not all variants will have all of the
// functionality defined here. 

//-----------------------------------------------------------------------------
// Cache dimensions.
// These really should be defined in plf_cache.h. If they are not, then provide
// a set of numbers that are typical of many variants.

#ifndef HAL_DCACHE_SIZE

// Data cache
#define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
#define HAL_DCACHE_WAYS                 2       // Associativity of the cache

// Instruction cache
#define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
#define HAL_ICACHE_WAYS                 2       // Associativity of the cache

#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))

#endif

// Defines for various SCORE cache operations
// this is a 5 bit field to define the operation
// of the I and D caches
#define HAL_SCORE_CACHE_PREFETCH_CACHELINE_I		0x00 /* 0 0 */
#define HAL_SCORE_CACHE_PREFETCH_LOCK_CACHELINE_I	0x01 /* 0 1 */
#define HAL_SCORE_CACHE_INVALID_UNLOCK_CACHELINE_I	0x02 /* 0 2 */
#define HAL_SCORE_CACHE_FILL_LIM_I					0x03 /* 0 3 */
#define HAL_SCORE_CACHE_REFILL_LIM_I				0x04 /* 0 4 */


#define HAL_SCORE_CACHE_PREFETCH_CACHELINE_D		0x08 /* 0 8 */
#define HAL_SCORE_CACHE_PREFETCH_LOCK_CACHELINE_D	0x09 /* 0 9 */
#define HAL_SCORE_CACHE_INVALID_UNLOCK_CACHELINE_D	0x0A /* 1 0 */
#define HAL_SCORE_CACHE_FILL_LDM_D					0x0B /* 1 1 */
#define HAL_SCORE_CACHE_WB_LDM_D					0x0C /* 1 2 */
#define HAL_SCORE_CACHE_WB_CACHEILNE_VALID_D		0x0D /* 1 3 */
#define HAL_SCORE_CACHE_WB_CACHEILNE_INVALID_D		0x0E /* 1 4 */

#define HAL_SCORE_CACHE_INVALID_ENTIRE_CACHE_I		0x10 /* 1 6 */
#define HAL_SCORE_CACHE_TOGGLE_CACHE_FUNCTION_I		0x11 /* 1 7 */

#define HAL_SCORE_CACHE_INVALID_ENTIRE_CACHE_D		0x18 /* 2 4 */
#define HAL_SCORE_CACHE_DRAIN_WRITE_BUFFER_D		0x1A /* 2 6 */
#define HAL_SCORE_CACHE_TOGGLE_WBUFFER_FUNCTION_D	0x1B /* 2 7 */
#define HAL_SCORE_CACHE_TOGGLE_CACHE_FUNCTION_D		0x1C /* 2 8 */
#define HAL_SCORE_CACHE_TOGGLE_WBACK_FUNCTION_D		0x1D /* 2 9 */
#define HAL_SCORE_CACHE_WB_ENTIRECACHE_VALID_D		0x1E /* 3 0 */
#define HAL_SCORE_CACHE_WB_ENTIRECACHE_INVALID_D	0x1F /* 3 1 */

 
//-----------------------------------------------------------------------------
// Address adjustment.
// Given an address and a size, these macros return the first 
// cacheline containing the requested range and a terminating address.

#define HAL_DCACHE_START_ADDRESS(_addr_) \
(((CYG_ADDRESS)(_addr_)) & ~(HAL_DCACHE_LINE_SIZE-1))

#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \
((CYG_ADDRESS)((_addr_) + (_asize_) + (HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1))

#define HAL_ICACHE_START_ADDRESS(_addr_) \
(((CYG_ADDRESS)(_addr_)) & ~(HAL_ICACHE_LINE_SIZE-1))

#define HAL_ICACHE_END_ADDRESS(_addr_, _asize_) \
((CYG_ADDRESS)((_addr_) + (_asize_) + (HAL_ICACHE_LINE_SIZE-1)) & ~(HAL_ICACHE_LINE_SIZE-1))

//-----------------------------------------------------------------------------
// Global control of data cache

// Enable the data cache
// There is no default mechanism for enabling or disabling the caches.
#ifndef HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE()							\
    CYG_MACRO_START                                 \
       	  asm volatile (						    \
			"nop;nop;nop;"	/*DCACHE is always*/	\
			"nop;nop;"		/*enable */             \
			);										\
    CYG_MACRO_END

#define HAL_DCACHE_ENABLE_DEFINED
#endif

// Disable the data cache
// At present , Score doesnot support disable D cache
#ifndef HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE()

#define HAL_DCACHE_DISABLE_DEFINED
#endif

#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
#define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;

#define HAL_DCACHE_IS_ENABLED_DEFINED
#endif

// Invalidate the entire cache
#ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
#define HAL_DCACHE_INVALIDATE_ALL()													\
	CYG_MACRO_START																	\
	     asm volatile (																\
			"la	r8, cyg_start;"		    											\
			"cache  0x18,[r8,0]; nop;"												\
			"nop; nop; nop; nop;"													\
			:																		\
			:																		\
			:"r8" 																	\
			);																		\
	CYG_MACRO_END

#define HAL_DCACHE_INVALIDATE_ALL_DEFINED
#endif

// Synchronize the contents of the cache with memory.
#ifndef HAL_DCACHE_SYNC_DEFINED
#define HAL_DCACHE_SYNC()															\
    CYG_MACRO_START																	\
       	  asm volatile (															\
			"la	r8, cyg_start;"		    											\
			"cache  0x1e,[r8,0]; nop;"												\
			"nop; nop; nop; nop;"													\
			"cache  0x1a,[r8,0];nop;"												\
			"nop; nop; nop; nop;"													\
			:																		\
			:																		\
			:"r8" 																	\
			);																		\
    CYG_MACRO_END

#define HAL_DCACHE_SYNC_DEFINED
#endif

// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)

// Set the data cache write mode
#ifndef HAL_DCACHE_WRITE_MODE_DEFINED
#define HAL_DCACHE_WRITE_MODE( _mode_ )                 \
    CYG_MACRO_START                                     \
	cyg_uint32 _cur_mode_;                              \
	HAL_DCACHE_QUERY_WRITE_MODE(_cur_mode_);            \
    if (_mode_ != _cur_mode_) {							\
        asm volatile ("la r8, cyg_start;"               \
                  "cache 0x1d,[r8,0];nop;nop;nop"       \
                  :										\
				  :										\
				  :"r8"									\
                  );									\
    }                                                   \
    CYG_MACRO_END

#define HAL_DCACHE_WRITE_MODE_DEFINED
#endif

#define HAL_DCACHE_WRITETHRU_MODE       0
#define HAL_DCACHE_WRITEBACK_MODE       1

// Get the current writeback mode - 
#ifndef HAL_DCACHE_QUERY_WRITE_MODE_DEFINED
#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ )           \
CYG_MACRO_START											\
    register cyg_uint32 reg;                            \
    asm volatile ("mfcr %0,cr4;"                        \
				  "nop;"                                \
				  "nop"                                 \
                  : "=r"(reg)                           \
                  :                                     \
        );                                              \
		_mode_ = ((reg & 0x80) != 0);                   \
CYG_MACRO_END

#define HAL_DCACHE_QUERY_WRITE_MODE_DEFINED
#endif
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
// This uses the fetch-and-lock cache operation.
#ifndef HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_LOCK(_base_, _asize_)									  \
    CYG_MACRO_START                                                           \
    cyg_uint32 __base = (cyg_uint32)(HAL_DCACHE_START_ADDRESS(_base_));       \
    cyg_int32 __count = ((HAL_DCACHE_END_ADDRESS(_base_,_asize_)-__base) / HAL_DCACHE_LINE_SIZE);                   \
    do {                                                                      \
        asm volatile ("mv   r8,%0;"	                                          \
                      "cache 0x9, [r8,0];"                                    \
                      "nop;nop;"		                                      \
                      "nop;nop;nop"                                           \
                      :							                              \