hal_intr.h

ecos下的gui开发源代码

#ifndef CYGONCE_HAL_HAL_INTR_H
#define CYGONCE_HAL_HAL_INTR_H

//==========================================================================
//
//      hal_intr.h
//
//      HAL Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    nickg
// Contributors: nickg, jskov,
//               gthomas, jlarmour
// Date:         2007-07-26
// Purpose:      Define Interrupt support
// Description:  The macros defined here provide the HAL APIs for handling
//               interrupts and the clock.
//              
// Usage:
//              #include <cyg/hal/hal_intr.h>
//              ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/hal.h>

#include <cyg/infra/cyg_type.h>

#include <cyg/hal/plf_intr.h>

//--------------------------------------------------------------------------
// SCORE vectors. 

// These are the exception codes presented in the Cause register and
// correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET

// RESET
#define CYGNUM_HAL_VECTOR_RESET		           0
// NMI exception
#define CYGNUM_HAL_VECTOR_NMI		           1
// INNSTRUCTION FETCH ADDRESS EXCEPTION
#define CYGNUM_HAL_VECTOR_ADEL_INSTRUCTION     2
// REV1
#define CYGNUM_HAL_VECTOR_REV1				   3
// REV2
#define CYGNUM_HAL_VECTOR_REV2				   4
// INNSTRUCTION FETCH BUS EXCEPTION
#define CYGNUM_HAL_VECTOR_BUSEL_INSTRUCTION    5
// INSTRUCTION P BIT ERROR
#define CYGNUM_HAL_VECTOR_PEL	               6
// Bus error (data load or store)
#define CYGNUM_HAL_VECTOR_BREAKPOINT           7
// System call
#define CYGNUM_HAL_VECTOR_CCU		           8
// Break point
#define CYGNUM_HAL_VECTOR_RI		           9
// Reserved instruction
#define CYGNUM_HAL_VECTOR_TRAP				   10
// Coprocessor unusable
#define CYGNUM_HAL_VECTOR_ADEL_DATA            11
// Arithmetic overflow
#define CYGNUM_HAL_VECTOR_ADES	               12
// Reserved
#define CYGNUM_HAL_VECTOR_REV3		           13
// REV1
#define CYGNUM_HAL_VECTOR_REV4				   14
// REV2
#define CYGNUM_HAL_VECTOR_REV5				   15

// Division-by-zero [reserved vector]
// This is caused by 'trap 0x7' which GCC puts in the code to check
// for division by zero. The break_vsr_springboard in vectors.S is the
// only caller of this vector.
#define CYGNUM_HAL_VECTOR_DIV_BY_ZERO          16

#define CYGNUM_HAL_VECTOR_CPE		           17

#define CYGNUM_HAL_VECTOR_BUSEL_DATA           18

#define CYGNUM_HAL_VECTOR_SWI		           19

#define CYGNUM_HAL_VECTOR_INTERRUPT	           20


#define CYGNUM_HAL_VSR_MIN                     CYGNUM_HAL_VECTOR_RESET

#define CYGNUM_HAL_VSR_MAX                     CYGNUM_HAL_VECTOR_INTERRUPT

#define CYGNUM_HAL_VSR_COUNT                   (CYGNUM_HAL_VSR_MAX-CYGNUM_HAL_VSR_MIN+1)


#define CYGNUM_HAL_EXCEPTION_MIN                CYGNUM_HAL_VSR_MIN
#define CYGNUM_HAL_EXCEPTION_MAX				CYGNUM_HAL_VSR_MAX
#define CYGNUM_HAL_EXCEPTION_COUNT        (1 + CYGNUM_HAL_EXCEPTION_MAX - \
                                           CYGNUM_HAL_EXCEPTION_MIN)


#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED

// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN                     0
#define CYGNUM_HAL_ISR_MAX                     63
#define CYGNUM_HAL_ISR_HALF                    32
#define CYGNUM_HAL_ISR_COUNT                   64

// The vector used by the Real time clock. The default here is to use
// interrupt 5, which is connected to the counter/comparator registers
// in many Score7 variants.

#ifndef CYGNUM_HAL_INTERRUPT_RTC
#define CYGNUM_HAL_INTERRUPT_RTC            56
#endif

#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED

#endif

//--------------------------------------------------------------------------
// Static data used by HAL

// ISR tables
externC volatile CYG_ADDRESS    hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];

// VSR table
externC volatile CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_MAX+1];

//--------------------------------------------------------------------------
// Default ISR
// The #define is used to test whether this routine exists, and to allow
// us to call it.

externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);

#define HAL_DEFAULT_ISR hal_default_isr

//--------------------------------------------------------------------------
// Interrupt state storage

typedef cyg_uint32 CYG_INTERRUPT_STATE;

//--------------------------------------------------------------------------
// Interrupt control macros
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
// that might otherwise cause following code to run in the wrong state or
// cause a resource conflict.
#ifndef CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED

#define HAL_DISABLE_INTERRUPTS(_old_)           \
{                                               \
    asm volatile (                              \
	"mfcr   r8,cr0; nop;"			\
	"mv	%0,r8;"				\
	"li	r9,0xfffffffe;"			\
	"and    r8,r8,r9; nop;"			\
	"mtcr   r8,cr0;"			\
	"nop!;nop!;nop!;nop!;nop!;"		\
	"ldi	r9,0x1; nop;"			\
	"and    %0,%0,r9;"			\
        : "=r"(_old_)                           \
        :                                       \
        : "r8","r9"                             \
        );                                      \
}

#define HAL_ENABLE_INTERRUPTS()                 \
{                                               \
    asm volatile (                              \
	"mfcr   r8,cr0; nop;"            	\
	"ldi	r9,1;"				\
        "or     r8,r8,r9;"                      \
        "mtcr   r8,cr0;"                 	\
	"nop!;nop!;nop!;nop!;nop!;"		\
        :                                       \
        :                                       \