hal_arch.h

ecos下的gui开发源代码

#ifndef CYGONCE_HAL_HAL_ARCH_H
#define CYGONCE_HAL_HAL_ARCH_H

//==========================================================================
//
//      hal_arch.h
//
//      Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    nickg
// Contributors: nickg, dmoseley, cWWeng
// Date:         2007-07-27
// Purpose:      Define architecture abstractions
// Usage:        #include <cyg/hal/hal_arch.h>
//              
//####DESCRIPTIONEND####
//
//==========================================================================

#ifndef __ASSEMBLER__
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

//--------------------------------------------------------------------------
// Processor saved states:
// The layout of this structure is also defined in "arch.inc", for assembly
// code. Do not change this without changing that (or vice versa).
// Notes: This structure is carefully laid out. It is a multiple of 8
// bytes and the pc and badvr fields are positioned to ensure that
// they are on 8 byte boundaries. 

typedef struct 
{
    // These are common to all saved states
    CYG_WORD32		d[32];          /* Data regs                    */
    CYG_WORD32      sr;             /* Status Reg                   */
    CYG_WORD32      cond;           /* Condition register           */
    CYG_WORD32      cause;          /* Exception cause register     */
    CYG_WORD32      excpvec;        /* Exception base 		*/
    CYG_WORD32      ccr;          /* Core control register       */
    CYG_WORD32      epc;          /* Cache control register       */
    CYG_WORD32      ema;          /* Cache control register       */
    CYG_WORD32      tlblock;      /* Cache control register       */
    CYG_WORD32      tlbpt;          /* Cache control register       */
    CYG_WORD32      peaddr;          /* Cache control register       */
    CYG_WORD32      tlbrpt;          /* Cache control register       */
    CYG_WORD32      pevn;          /* Cache control register       */
    CYG_WORD32      pectx;          /* Cache control register       */
    CYG_WORD32      limpfn;          /* Cache control register       */
    CYG_WORD32      ldmpfn;          /* Cache control register       */
    CYG_WORD32      prev;          /* Cache control register       */
    CYG_WORD32      dreg;          /* Cache control register       */
    CYG_WORD32		pc;             /* Program Counter              */
    CYG_WORD32		dsave;             /* hi word of mpy/div reg       */
    CYG_WORD32		counter;             /* lo word of mpy/div reg       */
    
    CYG_WORD32      ldcr;         /* Vector number                */
    CYG_WORD32      stcr;         /* Vector number                */


    CYG_WORD32		ceh;          /* Bad virtual address reg      */
    CYG_WORD32		cel;          /* Bad virtual address reg      */
} HAL_SavedRegisters;

//--------------------------------------------------------------------------
// Exception handling function.
// This function is defined by the kernel according to this prototype. It is
// invoked from the HAL to deal with any CPU exceptions that the HAL does
// not want to deal with itself. It usually invokes the kernel's exception
// delivery mechanism.

externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );

//--------------------------------------------------------------------------
// Bit manipulation macros

externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);

#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);

#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);

//--------------------------------------------------------------------------
// Context Initialization


// Optional FPU context initialization

#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )


// Initialize the context of a thread.
// Arguments:
// _sparg_ name of variable containing current sp, will be written with new sp
// _thread_ thread object address, passed as argument to entry point
// _entry_ entry point address.
// _id_ bit pattern used in initializing registers, for debugging.
#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )                     \
{                                                                                       \
    register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56;                                    \
    register HAL_SavedRegisters *_regs_;                                                \
    int _i_;                                                                            \
    _sp_ = _sp_ & 0xFFFFFFF0;                                                           \
    _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0);  \
    for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_;                      \
    HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ );                                        \
    (_regs_)->d[0] = (CYG_WORD)(_sp_);       /* SP = top of stack      */      \
    (_regs_)->d[4] = (CYG_WORD)(_thread_);   /* R4 = arg1 = thread ptr */      \
    (_regs_)->cel = 0;                                 /* LO = 0                 */      \
    (_regs_)->ceh = 0;                                 /* HI = 0                 */      \
    (_regs_)->d[2] = (CYG_WORD)(_sp_);       /* BP = top of stack      */      \
    (_regs_)->d[3] = (CYG_WORD)(_entry_);    /* RA(d[31]) = entry point*/      \
    (_regs_)->pc = (CYG_WORD)(_entry_);               /* PC = entry point       */      \
    (_regs_)->epc = (CYG_WORD)(_entry_);               /* PC = entry point       */      \
    (_regs_)->sr  = 0x00000001;                       /* SR = ls 3 bits only    */      \
    _sparg_ = (CYG_ADDRESS)_regs_;                                                      \
}

//--------------------------------------------------------------------------
// Context switch macros.
// The arguments are pointers to locations where the stack pointer
// of the current thread is to be stored, and from where the sp of the
// next thread is to be fetched.

externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
externC void hal_thread_load_context( CYG_ADDRESS to )
    __attribute__ ((noreturn));

#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
        hal_thread_switch_context( (CYG_ADDRESS)_tspptr_,               \
                                   (CYG_ADDRESS)_fspptr_);

#define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
        hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );

//--------------------------------------------------------------------------
// Execution reorder barrier.
// When optimizing the compiler can reorder code. In multithreaded systems
// where the order of actions is vital, this can sometimes cause problems.
// This macro may be inserted into places where reordering should not happen.
// The "memory" keyword is potentially unnecessary, but it is harmless to
// keep it.

#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )

/* CWWeng 2006/9/15 : Macros for distinguishing 32/16/PCE instructions */
#define INS_G_PBITS(_i)         ((((_i) >> 31) << 1) | BU_G_BIT(_i,15))

#define BU_G_BIT(_i,_n)             BU_G_FLD(_i, _n, _n)
#define BU_G_FLD(_i,_ms,_ls)        (((_i)<<(31-(_ms))) >> (31- (_ms) + (_ls))

#define INS_PBITS_32            0x3
#define INS_PBITS_16            0x0
#define INS_PBITS_PCE           0x1

//--------------------------------------------------------------------------
// Breakpoint support
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
// happen if executed.
// HAL_BREAKINST is the value of the breakpoint instruction and
// HAL_BREAKINST_SIZE is its size in bytes.
// HAL_BREAKINST_TYPE is the type.


//Disable SJTAG module  -- set DREG(cr29) IceDis bit29 to 1

#define HAL_BREAKPOINT(_label_)                 \
asm volatile (" .globl  " #_label_ ";"	\
		"mfcr   r8,cr29; nop;"	\
		"li     r9,0x20000000;"	\
		"or     r8,r8,r9; nop;"	\
		"mtcr   r8,cr29; nop;"	\
	#_label_":"                       \
              	" sdbbp   1;"           \
                ::: "r8","r9"		\
    );


#define HAL_BREAKINST           0x80018006	/* sdbbp 1   */
#define HAL_BREAKINST_16	0x600a		/* sdbbp 1 (16 bit mode) */
//#define HAL_BREAKINST           0x80008402	/* syscall 1 */

#define HAL_BREAKINST_SIZE      4

#define HAL_BREAKINST_TYPE      cyg_uint32

externC HAL_BREAKINST_TYPE score32_break_inst;
externC HAL_BREAKINST_TYPE score16_break_inst;

#ifdef HAL_BREAKINST_ADDR
#undef HAL_BREAKINST_ADDR
#define HAL_BREAKINST_ADDR(x) (((x)==4)? \
                              ((void*)&score32_break_inst) : \
                              ((void*)&score16_break_inst))
#else
#define HAL_BREAKINST_ADDR(x) (((x)==4)? \
                              ((void*)&score32_break_inst) : \
                              ((void*)&score16_break_inst))
#endif