arch.inc

ecos下的gui开发源代码

	nop
	.endm
	
	# Return from exception.
	.macro	hal_cpu_eret pc,sr
	ori     \sr,2                       # prevent interrupts until eret
	mtcr	\sr,CP0_STATUS			# put SR back
	nop
	nop
	nop
	nop
	nop
	mtcr	\pc,CP0_EPC			# put PC in EPC
	nop
	nop
	nop
	nop
	nop
# CWWeng 2006/2/16	
#	sync					# settle things down
#	eret					# return
	nop					# just to be safe
	.endm
	
##-----------------------------------------------------------------------------
# Default SCORE interrupt decoding macros. This uses the basic interrupt
# support provided by CP0 in the cause and status registers. If there is
# a more complex external interrupt controller, or the default stuff is
# interpreted differently then these macros will be 
# overridden and CYGPKG_HAL_SCORE_INTC_DEFINED will be defined.

#ifndef CYGPKG_HAL_SCORE_INTC_DEFINED

#ifndef CYGPKG_HAL_SCORE_INTC_INIT_DEFINED
	# initialize all interrupts to disabled
	.macro	hal_intc_init
	.endm
#endif

#ifndef CYGPKG_HAL_SCORE_INTC_DECODE_DEFINED
	.macro	hal_intc_decode vnum,tsr
	mfcr	\tsr,CP0_CAUSE		# get cause register
	nop				# delay slot
	srli	\tsr,\tsr,18		# shift interrupt bits down  CWWeng 2006/3/10 10->18
	andi	\tsr,0x3f		# isolate 6 interrupt bits
	mv	\vnum,\tsr		
	.endm
#endif

#ifndef CYGPKG_HAL_SCORE_INTC_TRANSLATE_DEFINED
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
	.macro	hal_intc_translate inum,vnum
	li	\vnum,0			# Just vector zero is supported
	.endm
#else			
	.macro	hal_intc_translate inum,vnum
	mv	\vnum,\inum			# Vector == interrupt number
	.endm
#endif
#endif

	.macro	hal_intc_decode_data
hal_intc_translation_table:	
	.byte	0, 0, 1, 0
	.byte	2, 0, 1, 0
	.byte	3, 0, 1, 0
	.byte	2, 0, 1, 0
	.byte	4, 0, 1, 0
	.byte	2, 0, 1, 0
	.byte	3, 0, 1, 0
	.byte	2, 0, 1, 0
	.byte	5, 0, 1, 0
	.byte	2, 0, 1, 0
	.byte	3, 0, 1, 0
	.byte	2, 0, 1, 0
	.byte	4, 0, 1, 0
	.byte	2, 0, 1, 0
	.byte	3, 0, 1, 0
	.byte	2, 0, 1, 0
	.endm
#endif

#------------------------------------------------------------------------------
# Register save and restore macros. These expect a pointer to a CPU save state
# area in the register \ptr. The GPR indicated by \reg will be saved into its
# slot in that structure.


	.macro sgpr reg,ptr
	sw	r\reg,[\ptr,\reg*score_regsize]
	.endm

	.macro lgpr reg,ptr
	lw	r\reg,[\ptr,\reg*score_regsize]
	.endm

	.macro ssp reg,ptr
	sw	\reg,[\ptr,0]
	.endm

	.macro lsp reg,ptr
	lw	\reg,[\ptr,0]
	.endm

	.macro spc reg,ptr
	sw	\reg,[\ptr,E_CP0_DEPC]
	.endm

#------------------------------------------------------------------------------
# FPU macros.
	# Default macros for non-fpu implementations
	
	.macro	hal_fpu_init
	.endm
		
	.macro	hal_fpu_save regs
	.endm

	.macro	hal_fpu_save_caller regs
	.endm

	.macro	hal_fpu_save_callee regs
	.endm

	.macro	hal_fpu_load_caller regs
	.endm
	
	.macro	hal_fpu_load_callee regs
	.endm
	
	.macro	hal_fpu_load regs
	.endm
	
#------------------------------------------------------------------------------
# MMU macros.
	
#ifndef CYGPKG_HAL_SCORE_MMU_DEFINED

	.macro	hal_mmu_init
	.endm

#endif	

#------------------------------------------------------------------------------
# MEMC macros.
	
#ifndef CYGPKG_HAL_SCORE_MEMC_DEFINED

	.macro	hal_memc_init
	.endm

#endif	
	
#------------------------------------------------------------------------------
# Cache macros.
	
#ifndef CYGPKG_HAL_SCORE_CACHE_DEFINED

	.macro	hal_cache_init

	.endm

#endif	

#------------------------------------------------------------------------------
# Diagnostics macros.
	
#ifndef CYGPKG_HAL_SCORE_DIAG_DEFINED

	.extern UartInit

	.macro	hal_diag_init
	.endm

	.macro	hal_diag_excpt_start
	.endm

	.macro	hal_diag_intr_start
	.endm

	.macro	hal_diag_restore
	.endm
#endif	

#------------------------------------------------------------------------------
# Timer initialization.
	
#ifndef CYGPKG_HAL_SCORE_TIMER_DEFINED

	.macro	hal_timer_init
	.endm

#endif	

#------------------------------------------------------------------------------
# Monitor initialization.
	
#ifndef CYGPKG_HAL_SCORE_MON_DEFINED

	.macro	hal_mon_init
	.endm

#endif	

#------------------------------------------------------------------------------
# Context save.

	.macro	save_gp_reg
        sw      AT, [SP,E_AT]
        sw      BP, [SP,E_BP]
        sw      LR, [SP,E_LR]
        sw      A0, [SP,E_A0]
        sw      A1, [SP,E_A1]
        sw      A2, [SP,E_A2]
        sw      A3, [SP,E_A3]
        sw      T0, [SP,E_T0]
        sw      T1, [SP,E_T1]
        sw      T2, [SP,E_T2]
        sw      T3, [SP,E_T3]
        sw      S0, [SP,E_S0]
        sw      S1, [SP,E_S1]
        sw      S2, [SP,E_S2]
        sw      S3, [SP,E_S3]
        sw      S4, [SP,E_S4]
        sw      S5, [SP,E_S5]
        sw      S6, [SP,E_S6]
        sw      S7, [SP,E_S7]
        sw      S8, [SP,E_S8]
        sw      S9, [SP,E_S9]
        sw      T4, [SP,E_T4]
        sw      T5, [SP,E_T5]
        sw      T6, [SP,E_T6]
        sw      T7, [SP,E_T7]
        sw      T8, [SP,E_T8]
        sw      T9, [SP,E_T9]
        sw      GP, [SP,E_GP]
        sw      JP, [SP,E_JP]
        sw      K0, [SP,E_K0]
        sw      K1, [SP,E_K1]
	.endm
	
	.macro	save_debug_cp_reg
	mfcr    T1, CP0_COND
        sw      T1, [SP,E_CP0_COND]
        mfcr    T1, CP0_EPC
        sw      T1, [SP,E_CP0_EPC]
        mfcr    T1, CP0_STATUS
        sw      T1, [SP,E_CP0_STATUS]
        #mfcr    T1, CP0_DREG
        #sw      T1, [SP,E_CP0_DREG]
        mfcr    T1, CP0_DEPC
        sw      T1, [SP,E_CP0_DEPC]
	.endm	

	.macro	save_scp_reg
		mfceh   T1
        sw      T1, [SP,E_SPR_HI]
		mfcel   T1
        sw      T1, [SP,E_SPR_LO]
        mfsr    T1, SR_CNT
        sw      T1, [SP,E_CP0_COUNTER]
        mfsr    T1, SR_LCR
        sw      T1, [SP,E_CP0_LDCR]
        mfsr    T1, SR_SCR
        sw      T1, [SP,E_CP0_STCR]
	.endm	

	.macro	restore_gp_reg
	lw      AT, [SP,E_AT]
        lw      BP, [SP,E_BP]
        lw      LR, [SP,E_LR]
        lw      A0, [SP,E_A0]
        lw      A1, [SP,E_A1]
        lw      A2, [SP,E_A2]
        lw      A3, [SP,E_A3]
        lw      T0, [SP,E_T0]
        lw      T1, [SP,E_T1]
        lw      T2, [SP,E_T2]
        lw      T3, [SP,E_T3]
        lw      S0, [SP,E_S0]
        lw      S1, [SP,E_S1]
        lw      S2, [SP,E_S2]
        lw      S3, [SP,E_S3]
        lw      S4, [SP,E_S4]
        lw      S5, [SP,E_S5]
        lw      S6, [SP,E_S6]
        lw      S7, [SP,E_S7]
        lw      S8, [SP,E_S8]
        lw      S9, [SP,E_S9]
        lw      T4, [SP,E_T4]
        lw      T5, [SP,E_T5]
        lw      T6, [SP,E_T6]
        lw      T7, [SP,E_T7]
        lw      T8, [SP,E_T8]
        lw      T9, [SP,E_T9]
        lw      GP, [SP,E_GP]
        lw      JP, [SP,E_JP]
        lw      K0, [SP,E_K0]
        lw      K1, [SP,E_K1]	
	.endm
		
	.macro	restore_scp_reg
        lw      T0, [SP, E_SPR_HI]
        mtceh   T0
        lw      T0, [SP, E_SPR_LO]
        mtcel   T0
        lw      T0, [SP, E_CP0_COUNTER]
        mtsr    T0, SR_CNT
        lw      T0, [SP, E_CP0_LDCR]
        mtsr    T0, SR_LCR
        lw      T0, [SP, E_CP0_STCR]
        mtsr    T0, SR_SCR
	.endm		
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_ARCH_INC
# end of arch.inc