arch.inc

ecos下的gui开发源代码

#ifndef CYGONCE_HAL_ARCH_INC
#define CYGONCE_HAL_ARCH_INC
##=============================================================================
##
##	arch.inc
##
##	SCORE assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): 	nickg
## Contributors:	nickg, dmoseley
## Date:	2007-07-26
## Purpose:	Architecture definitions.
## Description:	This file contains various definitions and macros that are
##              useful for writing assembly code for the SCORE7 CPU family.
## Usage:
##		#include <cyg/hal/arch.inc>
##		...
##		
##
######DESCRIPTIONEND####
##
##=============================================================================

#include <cyg/hal/score.inc>
	
##-----------------------------------------------------------------------------	
## Set up the value for the initial status register


# Either the variant or platform may define an INITIAL_SR of its
#own. If not then provide a default value here.

#ifndef INITIAL_SR

# Both the variant and platform HALs have the option to add some bits
# to the default status register. If they do not choose to do so,
# supply default zeroes here.

# ifndef INITIAL_SR_VAR
#  define INITIAL_SR_VAR 0x00000000
# endif
# ifndef INITIAL_SR_PLF
#  define INITIAL_SR_PLF 0x00000000
# endif

#if defined(CYG_HAL_STARTUP_RAM) || defined(CYG_HAL_STARTUP_ROMRAM)
# if defined(CYGPKG_HAL_SCORE_SIM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR)
#  define INITIAL_SR_ARCH 	0x00000001 /* CP0 usable, Ints enabled, master interrupt disable */
# else
#  define INITIAL_SR_ARCH 	0x00000001	/* as above + ROM vectors used	*/
# endif	
#elif defined(CYG_HAL_STARTUP_ROM)
# define INITIAL_SR_ARCH	0x00000001	/* as above + ROM vectors used	*/
#endif

#define INITIAL_SR 	(INITIAL_SR_ARCH|INITIAL_SR_VAR|INITIAL_SR_PLF)

#endif

##-----------------------------------------------------------------------------
## Setup the initial value for the config0 register


// general registers symbolic
#define    SP        r0
#define    AT        r1
#define    BP        r2
#define    LR        r3
#define    A0        r4
#define    A1        r5
#define    A2        r6
#define    A3        r7
#define    T0        r8
#define    T1        r9
#define    T2        r10
#define    T3        r11
#define    S0        r12
#define    S1        r13
#define    S2        r14
#define    S3        r15
#define    S4        r16
#define    S5        r17
#define    S6        r18
#define    S7        r19
#define    S8        r20
#define    S9        r21
#define    T4        r22
#define    T5        r23
#define    T6        r24
#define    T7        r25
#define    T8        r26
#define    T9        r27
#define    GP        r28
#define    JP        r29
#define    K0        r30
#define    K1        r31

// CP0 register define
#define CP0_STATUS   cr0
#define CP0_COND     cr1
#define CP0_CAUSE    cr2
#define CP0_EXCPVEC  cr3
#define CP0_CCR      cr4
#define CP0_EPC      cr5
#define CP0_BADVA    cr6
#define CP0_WIRE     cr7
#define CP0_INDEX    cr8
#define CP0_CONTEXT  cr9
#define CP0_RANDOM   cr10
#define CP0_ENTRYHI  cr11
#define CP0_ENTRYLO  cr12
#define CP0_FMARLO   cr13
#define CP0_FMARHI   cr14
#define CP0_FMCR     cr15
#define CP0_FFMR     cr16
#define CP0_LLADDR   cr17
#define CP0_PREV     cr18
#define CP0_DREG     cr29
#define CP0_DEPC     cr30
#define CP0_DSAVE    cr31
#define SPR_HI       sr1
#define SPR_LO       sr2

//specification define
#define SR_CNT       sr0
#define SR_LCR       sr1
#define SR_SCR       sr2

#define E_SP            0*4
#define E_AT            1*4
#define E_BP            2*4
#define E_LR            3*4
#define E_A0            4*4
#define E_A1            5*4
#define E_A2            6*4
#define E_A3            7*4
#define E_T0            8*4
#define E_T1            9*4
#define E_T2            10*4
#define E_T3            11*4
#define E_S0            12*4
#define E_S1            13*4
#define E_S2            14*4
#define E_S3            15*4
#define E_S4            16*4
#define E_S5            17*4
#define E_S6            18*4
#define E_S7            19*4
#define E_S8            20*4
#define E_S9            21*4
#define E_T4            22*4
#define E_T5            23*4
#define E_T6            24*4
#define E_T7            25*4
#define E_T8            26*4
#define E_T9            27*4
#define E_GP            28*4
#define E_JP            29*4
#define E_K0            30*4
#define E_K1            31*4

#define E_CP0_STATUS    32*4
#define E_CP0_COND      33*4
#define E_CP0_CAUSE     34*4
#define E_CP0_EXCPVEC   35*4
#define E_CP0_CCR       36*4

#define E_CP0_EPC       37*4
#define E_CP0_EMA       38*4
#define E_CP0_TLBLOCK   39*4
#define E_CP0_TLBPT     40*4
#define E_CP0_PEADDR    41*4
#define E_CP0_TLBRPT    42*4
#define E_CP0_PEVN      43*4
#define E_CP0_PECTX     44*4
#define E_CP0_LIMPFN    45*4
#define E_CP0_LDMPFN    46*4
#define E_CP0_PREV      47*4
#define E_CP0_DREG      48*4
#define E_CP0_DEPC      49*4
#define E_CP0_DSAVE     50*4
#define E_CP0_COUNTER   51*4
#define E_CP0_LDCR      52*4
#define E_CP0_STCR      53*4
#define E_SPR_HI        54*4
#define E_SPR_LO        55*4

#define SCORE_STACK_SIZE          56*4 /* must be even */


##-----------------------------------------------------------------------------
## SCORE thread and interrupt saved state. This must match the layout of the
## HAL_SavedRegisters in hal_arch.h. Do not change this without changing the
## layout there, or viceversa.	

# Size of registers that change size between 32 and 64 bit implementations
# define score_regsize 	4

# Size of registers that stay the same size in all implementations
# define score_regsize32	4

##-----------------------------------------------------------------------------
## Minimal stack frame size uses to call functions from asm.
	
#define score_stack_frame_size		32	// 4 (64 bit) args worth

##-----------------------------------------------------------------------------
## CPU specific macros. These provide a common assembler interface to
## operations that may have CPU specific implementations on different
## variants of the architecture.		
	
	# Initialize CPU
	.macro	hal_cpu_init
	.endm

	# Enable interrupts
	.macro hal_cpu_int_enable tsr
	mfcr	\tsr,CP0_STATUS
	nop
	nop
	ori	\tsr,0x0001		# set IE bit
	nop
	mtcr	\tsr,CP0_STATUS
	nop
	nop
	nop
	nop
	nop
	.endm		


	# Disable interrupts
	.macro hal_cpu_int_disable tsr1,tsr2
	mfcr	\tsr1,CP0_STATUS
	nop
	ldis	\tsr2,0xffff
	ori	\tsr2,0xfffe
	nop
	and	\tsr1,\tsr1,\tsr2
	nop
	mtcr	\tsr1,CP0_STATUS
	nop
	nop
	nop
	nop
	nop
	.endm	

	# Merge the interrupt enable state of the status register in
	# \sr with the current sr.
#define HAL_SR_INT_MASK	0x00000001		// IEC

	.macro	hal_cpu_int_merge sr,tsr1,tsr2
	mfcr	\tsr1,CP0_STATUS			# V0 = current SR
	la	\tsr2,HAL_SR_INT_MASK		# V1 = SR interrupt bits mask
	and	\sr,\sr,\tsr2			# Isolate interrupt bits of \sr
	not	\tsr2,\tsr2				# Invert mask
	and	\tsr1,\tsr1,\tsr2			# V0 = current SR except int bits
	or	\tsr1,\tsr1,\sr			# V0 = New SR
	nop
	nop
	mtcr	\tsr1,CP0_STATUS			# Return to SR
	nop
	nop
	nop
	nop
	nop
	.endm

	# Enable further exception processing, and disable
	# interrupt processing.

	.macro hal_cpu_except_enable tsr1,tsr2
	mfcr	\tsr1,CP0_STATUS
	la	\tsr2,0xFFFFFFFE
	and	\tsr1,\tsr1,\tsr2		# clear EXL, ERL and IE bits	
	mtcr	\tsr1,CP0_STATUS
	nop
	nop
	nop
	nop